本論文的第一部份提出一個應用於快閃記憶體昇壓電路之限壓電路，我們利用電晶體的門檻電壓和迴授電路，即時地調整充電泵的充電時脈擺幅，穩定充電泵的輸出電壓，且避免了由線性昇壓率產生的不需要電壓。不僅如此，更防止了記憶體核心可能的損壞，而功率消耗也比傳統架構節省。

第二個部分是使用切換電流實現之3位元真實亂數產生器，我們利用一個數位的平均器將參數B平均的分佈在整個區間，因而可以解決先前設計的『彩色』雜訊問題，且我們提出的設計是可動態地調整演算法參數。

The first topic of this thesis is a voltage boost level clamping circuit for a flash memory which utilizes an implicit feedback loop as well as MOS transistors with different threshold voltages. The proposed design can be added to charge pumps to stabilize the output voltage. The unwanted output voltage spikes introduced by the linear pumping ratio are prevented. Not only are possible damages to memory cores avoided, the power disspation is reduced in contrast with prior regulator methods.

The second topic is a switch-current 3-bit CMOS wideband random signal generator, which utilizes a digital normalizer to flatten the distribution of the probability in the entire range of B parameter. The “colored” random numbers problem in prior designs is resolved. In addition, the coefficients of the proposed design are dynamically adjustable.

摘要 i
Abstract ii
第一章 簡介 1
1.1 論文動機與目的 1
1.2 相關研究討論 4
1.3 論文大綱 7
第二章 應用於快閃記憶體昇壓電路之限壓電路 8
2.1 簡介 8
2.2 原理說明 9
2.3 電路架構設計 12
2.3.1 Vc產生電路 12
2.3.2 取樣時脈電路 15
2.3.3 充電泵電路 16
2.4 模擬結果 20
2.4.1 Vc產生電路 20
2.4.2 取樣時脈電路 21
2.4.3 充電泵電路 22
2.4.4 預計規格 27
2.5 佈局 30
2.6 測試結果 31
2.6.1 測試方法 31
2.6.2 實測結果 32
2.6.3 量測結果討論 35
2.7 結論 36
第三章 使用切換電流實現之三位元真實亂數產生器 37
3.1 簡介 37
3.2 研究動機 37
3.3 架構原理與電路設計 38
3.3.1 離散時間渾沌演算法說明 38
3.3.2 1位元真實亂數產生器 41
3.3.3 3位元真實亂數產生器 41
3.3.4 線性取樣與保持電路 42
3.3.5 非線性決定電路 43
3.3.6 平均器與相位產生器 45
3.4 模擬結果 47
3.4.1 非線性決定電路 47
3.4.2 1位元真實亂數產生器 48
3.4.3 3位元真實亂數產生器 51
3.4.4 效能比較 55
3.5 佈局 56
3.6 結論 57
第四章 結論 58
參考文獻 62

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