在微處理器系統中，指令流與資料流的頻寬不足一直是限制整個系統效能的主要原因，雖然使用Cache可以有效的舒緩此問題，但處理器卻依然無法在一個時脈週期內取得資料，而由於Cache的硬體代價過高且常是整個系統中功率消耗的主要部分，也造成了Cache在嵌入式系統中存在著應用上的瓶頸。緩衝器機制可以簡單的硬體增加頻寬提升效能，如Loop buffer或Prefetch buffer，其機制著重於連續資料空間的暫存，而對如分支指令出現的非連續資料空間的存取，並無法充分利用此資料取用的區域性。在本論文中我們提出了一個新的緩衝器機制，稱為ABP buffer，其是由一緩衝機制和一預取機制所構成，緩衝機制能有效的將不連續的資料空間保留在緩衝器空間，且具有適於硬體實現的資料置換策略，而預取機制則利用資料命中的時間，預取未來最有可能被使用的資料。模擬及實作結果顯示，此機制可以有效的以極低的硬體代價得到很高的效能，且其控制機構只佔整個硬體的4%，因此此機制可以極低的硬體負擔實現。

In the microprocessor system, the bandwidth problems of instruction stream and data stream are the main causes that limit the performance of the system. Although cache can effectively smooth this problem, the processor still needs more than one clock cycle to get the data. The large hardware cost and power consumption also limit the cache in the embedded system applications. The buffering techniques, such as the loop buffer and the prefetch buffer, can improve the performance in low hardware. Their mechanisms emphasize on the buffering of the continuous data space. For the non-continuous data space accesses caused by the branch instructions, they cannot exploit the reference localities. In this thesis, we propose a new buffering mechanism called as the ABP buffer, which is composed of a buffering mechanism and a prefetching mechanism. The buffering mechanism can effectively buffer the non-continuous data space and replace the buffer lines in a replacement policy, which is suitable for hardware realization. The prefetching mechanism exploits the hit time to prefetch the data that can be used in near future. The simulation and implement results show that the ABP buffer can gain high performance in low hardware and the control parts of the mechanism only occupy 4% of the total hardware.

誌謝 i
摘要 ii
ABSTRACT iii
Contents iv
List of Figures vi
List of Tables vii
Chapter 1 Introduction 1
1.1 Bandwidth Problems of the Instruction and Data Stream 2
1.2 Real World Problems of the Cache System 3
1.3 Motivations and Purposes 3
1.4 Organization of This Thesis 5
Chapter 2 Survey 6
2.1 Study of Program Behavior 6
2.1.1 Property of Program Locality 6
2.1.2 Stream Characteristics of Object Oriented Language 7
2.1.3 Stream Characteristics of Multimedia Application 8
2.2 Related Research and Technology 9
2.2.1 Loop buffer 9
2.2.2 Prefetch Buffer 11
2.2.3 Target Instruction Buffer 12
2.2.4 Caches with multiple line buffers 13
Chapter 3 Design of the ABP buffer 15
3.1 Primitive ABP buffer 15
3.2 Extended ABP Buffer 24
3.2.1 The AB Decision Tree 25
3.2.2 Adjustment Algorithm and B Search Algorithm 28
3.3 The hardware architecture of the ABP buffer 32
Chapter 4 Simulation and Evaluation 36
4.1 Simulation Environment 36
4.1.1 Simulator 37
4.1.2 Benchmark Programs 38
4.2 Simulation Results and Evaluation 40
4.2.1 Impact of Line Sizes and Depth 40
4.2.2 Replacement Policy Analysis 43
4.2.3 Performance in burst mode 44
4.2.4 Performance Analysis 48
4.3 Verification 49
Chapter 5 Concluding Remarks 52
Reference 54

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