現今的DSP處理器設計常利用VLIW架構提高指令執行之並行度，以達到提高效能的目的。提高指令並行度的瓶頸有二，一是硬體資源是否足以同時處理所有的平行指令，二是由於指令間的相依關係所以無法平行處理；本論文針對ＦＦＴ演算法設計了一個VLIW架構之運算核心DVBTDSP，並利用軟體排程(Software pipelining)的方式將指令迴圈重新排程以達到在處理FFT之蝴蝶運算時具有最佳之指令並行度，另外為了能提供順暢的資料流，本論文針對FFT向量運算之特性，改良傳統DSP的餘數定址(modulo addressing)之運算機制，使得原本離散的向量能被視為一新的連續向量，避免了因向量中斷所造成的管線延遲，根據模擬分析的結果，此架構在處理FFT運算時跟C6200相比只需要其1/2的運算時間，在做其他演算法如FIR，IIR，DCT也有不亞於C6200的效能。

In order to improving the performance for real-time application, current digital signal processors use VLIW architectures to increase the degree of instruction level parallelism (ILP). Two factors will limit the ILP, one is enough hardware resource for all parallel instructions. Another is the dependence relations between instructions. This thesis designs a VLIW architecture processing core called DVBTDSP molded by FFT algorithm and uses the software pipelining mechanism to schedule the loop to achieve the highest ILP degree when used to execute FFT butterfly operations. Furthermore, in order to provide the smooth data stream for pipeline operations, we design a mechanism to improve the modulo addressing, which will collect the discrete vectors into one continuous vector. The simulation results show that the DVBTDSP has double performance of the C6200 for the FFT processing, and has good performance for FIR, IIR and DCT algorithm computing.

摘要 i
ABSTRACT ii
Contents iii
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 The Development of DSP and Vector Processors 3
1.2 Standard DSP Architecture 4
1.3 Motivation and Goal 6
Chapter 2 Survey 8
2.1 VLIW 8
2.2 Basic Compiler ILP 9
2.3 Vector Processors 13
2.4 Current DSP processor with vector computing (VFP, C3x, C6x) 14
Chapter 3 Design of an Instruction Pipeline Decoder 20
3.1 The Characteristics of Arm Introduction Set 21
3.1.1 Instruction types 21
3.1.2 Multi-cycle instruction 22
3.1.3. Instruction stream 22
3.1.4. Forwarding controller 25
3.2 A Single Instruction Pipeline Decoder Design 26
3.2.1 Architecture 26
3.2.2 Resolution unit 28
3.3 Decoder design in VLIW DSP architecture 29
Chapter 4 Vectorized computing algorithm in VLIW architecture 31
4.1 FFT algorithm with DSP processing 31
4.2 Vectorized code scheduling 36
4.3 Circular Index Register setting instructions 39
4.4 Conditional load instruction 40
4.5 Modulo addressing mode 41
4.6 The Architecture of DVBTDSP 46
4.7 Super Element Architecture 48
4.7.1 ALUL 50
4.7.2 ALUR & MUL 51
4.7.3 Load 53
4.7.4 Store 55
4.7.5 Register File 56
Chapter 5 Verification and Analysis result 59
5.1 Verification environment 61
5.2 Synthesis results 62
5.3 Analysis results 65
Chapter 6 Conclusions and Future Work 72
Appendix 74
Reference 82

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