現今高速數位系統，體積小是一大趨勢，因此，在設計電路時，不得不考慮如何去縮小電路所佔用之面積。但在縮小電路所佔用之面積的同時，亦使訊號在傳輸之過程中不會失真或是常失真不嚴重，使系統仍可以正常工作並判斷訊號，在這樣的需求下，蜿延線則是常被使用於設計中。在此提出一有效之方法來設計蜿延線，配合FDTD以及HFSS之模型來預測其電路之行為與特徵；同時，加入差模蜿延線與一般之蜿延線做比較，並討論其電路行為與現象。本篇論文最重要的是提供了一個完整的單根蜿延線以及差模蜿延線的設計流程，以期能讓設計者有一完整的法則可以遵行而設計出理想且實用之蜿延線。

Small size of electronic product with high layout density is the future trend in today’s high speed digital circuit design. A circuit designer is obliged to optimize the best solution of circuit layout in a limited area in order to both keep a good signal integrity（SI）, and save the layout space. Meander delay line is one of the challenging topic in high-speed circuit. In this dissertation, a effective method is provided to design a meander delay line, and FDTD and HFSS are matched up to predict the behavior and the character of the meander delay line; the differential meander delay line is compared with the single meander delay line, and the behavior and phenomena of the differential meander delay line are discussed. To reduce couple power, the differential meander line of design would be a new thinking. The most important point in this thesis, the complete flows of designing single meander lines and differential meander lines are provided, and designer could follow the steps of the proposed method to design a perfect and practical meander line with both keeping good SI and using least layout space. The effect of the design parameters of the meander line on the signal quality both in time-domain and frequency-domain is theoretically and experimentally investigated. FDTD method and the commercial tool HFSS are employed for the numerical study in this work.

第一章 序
1.1 研究目的與方法
1.2 論文大綱
第二章 FDTD演算法
2.1 從馬克斯威爾方程式到FDTD演算法
2.1.1 三維方程式
2.1.2 中央差分與Yee演算法
2.2 數值穩定
2.3 介質處理
2.4 波源條件
2.5 吸收邊界條件
2.5.1 完美匹配層吸收邊界
2.5.2 非分離埸完美匹配層
2.6 集總元件
2.6.1 FDTD演算法延伸至電路元件
2.6.2 電阻
2.6.3 阻抗性電壓源
2.7 電腦演算法與FDTD方法
2.7.1 前置過程
2.7.2 進行時間步階
2.7.3 紀錄埸值
第三章 單根蛇行訊號延遲線之原理
3.1 基本結構
3.2 蛇行訊號延遲線之現象
3.3 耦合
第四章 多層板之模擬
4.1 結構及問題描述
4.1.1 測試結構-FDTD與HFSS
4.1.2 測試結構-時域
4.1.3 測試結構-頻域
4.1.4 問題討論與方向
4.1.5 截止頻率點
4.2 結果比較與初步設計之概念
4.3 其他結構因素之影響
4.3.1 折數之變化
4.3.2 整體比較
4.4 比例為3之現象
4.5 單根蛇行訊號延遲線之電路模型
4.5.1 基本理論
4.5.2 Spice之電路模型
4.5.3 電路模型討論
4.6 單根蛇行訊號延遲線之設計流程
第五章 差模蛇訊號延遲線之原理
5.1 基本結構
5.2 耦合
第六章 差模蛇行訊號延遲線
6.1 結構與問題描述
6.1.1 測試結構-FDTD與HFSS
6.1.2 測試結構-時域
6.1.3 測試結構-頻域
6.1.4 問題討論與方向
6.1.5 截止頻率點
6.2 結果比較與初步設計之概念
6.3 其他結構因素之影響
6.3.1 折數之變化
第七章 結論

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