本論文包含兩個主題：使用箝制動態閘極偏壓產生器之全雙向混合電壓共容輸出入緩衝器與具校正功能之全雙向混合電壓共容輸出入緩衝器。
第一個主題探討一混合電壓共容輸出入緩衝器，以2P4M 0.35- μm CMOS製程實現。藉由一以閉迴路架構及電晶體箝制技術構成之低功率偏壓電路，電壓源準位偵測器電路，電壓準位轉換電路，邏輯開關電路和動態驅動偵測器電路，構成一個具有低功\率直流偏壓產生特性之箝制動態閘極偏壓產生器。本設計將可傳輸及接收5/ 3.3/ 1.8 V電壓準位之數位信號，且不會有任何閘極氧化層過度應力與漏電流，適用於不同電壓介面應用。
第二個主題探討一適用電壓範圍0.9至5 V之混合電壓共容輸出入緩衝器，以2P4M 0.35 μm CMOS製程實現。藉由一新型動態閘極偏壓產生器，提供一以堆疊式PMOS及堆疊式NMOS構成之輸出級電路適當的閘極偏壓，本設計將可傳輸一較高電壓信號(VDDH)。本設計提出一新型浮動N型井電路以消除輸出級PMOS基底效應。並使用一動態驅動偵測電路，用以平衡輸出級PMOS及NMOS導通電壓。為了達到大輸入範圍電壓應用，本設計輸入緩衝器則加入一邏輯校正電路，將可接收0.9至5 V電壓信號。

The thesis is composed of two topics : a fully bidirectional mixed-voltage-tolerant I/O buffer using a clamping dynamic gate bias generator and a wide range fully bidirectional mixed-voltage-tolerant I/O buffer with a calibration function.
The first topic, a mixed-voltage-tolerant I/O buffer implemented in 2P4M 0.35 μm CMOS process, comprises a low-power bias circuit with clamping transistors in a feedback loop, a power supply level detector circuit, a voltage level converter circuit, a logic switch circuit, a dynamic driving detector circuit, and a clamping dynamic gate bias generator. The proposed design can transmit and receive digital signals with voltage levels of 5/3.3/1.8 V without any gate-oxide overstress and leakage current path in different voltage interface applications.
The second topic, a 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage-tolerant I/O buffer carried out in 2P4M 0.35 μm CMOS technology, contains a dynamic gate bias generator to provide appropri¬ate gate voltages for the output stage composed of stacked PMOS and stacked NMOS, an I/O buffer which can transmit the signal with a higher voltage level (VDDH), a floating N-well circuit to remove the body effect at the output PMOS, and a dynamic driving detector to balance the turn-on voltages for the pull-up PMOS and pull-down NMOS in the output stage. The duty cycle of the output signal of the proposed I/O buffer can then be equalized even if the output stage power supply is biased at a low voltage. In order to adapt to wide range input voltage applications, a logic calibration circuit is added in the input buffer.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 viii
表目錄 xii
第一章 概論 1
1.1 前言 1
1.2 相關技術與文獻探討 2
1.3 研究動機 5
1.4 論文大綱 8
第二章 靜電放電防護電路 9
2.1 簡介 9
2.2 電路架構 10
2.3 電路設計 11
2.3.1 通道長度 11
2.3.2 多晶矽間距（poly-silicon spacing） 12
2.4 晶片佈局 13
2.4.1 佈局考量 13
2.4.2 佈局平面圖 13
2.5 晶片量測 14
2.6 晶片實作量測之結論與討論 17
第三章 使用箝制動態閘極偏壓產生器之全雙向混合電壓共容輸出入緩衝器 20
3.1 簡介 20
3.2 電路架構 21
3.2.1 輸出緩衝器 21
3.2.2 輸入緩衝器 22
3.3 電路設計 24
3.3.1 預先驅動電路 26
3.3.2 輸出級電路 27
3.3.3 閘極電壓追蹤電路 28
3.3.4 浮動N型井電路 29
3.3.5 動態閘極偏壓產生器電路 30
3.4 預計規格 35
3.4.1 效能比較 36
3.5 晶片佈局 37
3.5.1 佈局考量 37
3.6 電路模擬與晶片量測 38
3.6.1 電路模擬結果 38
3.6.2 晶片實作與量測結果 40
3.6.3 靜電放電防護能力量測結果 44
3.7 晶片實作量測之討論 45
第四章 具校正功能之全雙向混合電壓共容輸出入緩衝器 46
4.1 簡介 46
4.2 電路架構 47
4.2.1 輸出緩衝器 47
4.2.2 輸入緩衝器 47
4.3 電路設計 49
4.3.1 浮動N型井電路 49
4.3.2 動態閘極偏壓產生器電路 52
4.3.3 靜電放電防護電路 56
4.3.4 輸入緩衝器電路 56
4.4 預計規格 57
4.4.1 效能比較 58
4.5 晶片佈局 59
4.5.1 佈局考量 59
4.6 電路模擬與晶片量測 60
4.6.1 電路模擬結果 60
4.6.2 晶片實作與量測結果 64
4.6.3 靜電放電防護能力量測結果 65
4.7 晶片實作量測之討論 65
第五章 結論及成果 66
參考文獻 68

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