非揮發性記憶體(NVM)目前在元件尺寸持續微縮下的需求為高密度記憶單元、低功率損耗、快速讀寫操作、以及良好的可靠度(Reliability)。傳統浮動閘極(floating gate)記憶體在操作過程中如果穿隧氧化層產生漏電路徑會造成所有儲存電荷流失回到矽基板，所以在資料保存時間(Retention)和耐操度(Endurance)的考量下，很難微繼續縮穿隧氧化層的厚度。非揮發性奈米點記憶體被提出希望可取代傳統浮動閘極記憶體，由於奈米點可視為電荷儲存層中彼此分離的儲存點，可以有效改善小尺寸記憶體元件多次操作下的資料儲存能力。近年來發展了許多方法來形成奈米點，一般而言，大多數的方法都需要長時間高溫的熱製程，這個步驟會影響現階段半導體製程中的熱預算和產能。
在本文中，主要提出三種不同結構的高介電係數穿隧氧化層(Al2O3, HfO2/Al2O3/HfO2, Al2O3/HfO2/Al2O3)來克服傳統非揮發性記憶體在微縮過程中會遭遇到的困難，我們首先利用單純的氧化鋁當作穿隧氧化層，並且在記憶體特性沒有減少太多的情況下，成功降低穿隧氧化層之等效厚度；接著利用凸狀能帶結構之穿隧氧化層(HfO2/Al2O3/HfO2)成功改善電子與電洞注入特性，提升其電荷儲存能力，並且減少穿隧氧化層之有效厚度；最後，利用凹狀能帶結構之穿隧氧化層(Al2O3/HfO2/Al2O3)成功在不影響電子與電洞注入特性情況化，使電荷儲存能力再度提升，並且減少穿隧氧化層厚度。我們所提出的奈米點結構與製造技術都可以應用於非揮性奈米點記憶體的製程技術同時也適用於現階段積體電路製程。

Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for the scaling down devices. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance characteristics. The nonvolatile nanocrystal memories are one of promising candidates to substitute for conventional floating gate memory, because the discrete storage nodes as the charge storage media have been effectively improve data retention under endurance test for the scaling down device. Many methods have been developed recently for the formation of nanocrystal. Generally, most methods need thermal treatment with high temperature and long duration. This procedure will influence thermal budget and throughput in current manufacture technology of semiconductor industry.
In this thesis, we used the three kind of high-k dielectric structure as the tunnel oxide (Al2O3, HfO2/Al2O3/HfO2, Al2O3/HfO2/Al2O3) to overcome the limitation of conventional NVMs during the scaling down process. First, we used Al2O3 as tunnel oxide. It observed that device of Al2O3 as tunnel oxide reduce equivalent thickness without lost retention too much. Then, we used HfO2/Al2O3/HfO2 as tunnel oxide. It observed the device of HfO2/Al2O3/HfO2 as tunnel oxide which had bigger window than the device used thermal oxide as tunnel oxide. Moreover it had better retention characteristics than the device used thermal oxide as tunnel oxide with a small charge lose rate. And it reduced equivalent thickness of SiO2.Final, we used Al2O3/HfO2/Al2O3 as tunnel oxide. It observed the device of Al2O3/HfO2/Al2O3 as tunnel oxide which had better retention characteristics than the device used HfO2/Al2O3/HfO2 as tunnel oxide without decrease the electron and hole injection. And we reduce equivalent thickness of SiO2 .

Contents
Chinese Abstract……………………………………………………..Ⅰ
English Abstract………………………………………………………..Ⅲ
Acknowledgement…………………………………………...V
Contents……………………………………………………....ⅤI
Table Captions……………………………………………………....IX
Figure Captions……………………………………………………....Ⅹ
Chapter 1 Introduction
1.1 Overview of Nonvolatile Memory……………………………........1
1.1.1 SONOS Nonvolatile Memory Devices…………………………............4
1.1.2 Nanocrystal Nonvolatile Memory Devices……………................................7
1.2 Organization of This Thesis……………………….................13
Chapter 2 Basic Principle of Nonvolatile Memory
2.1Introduction.........................................................................................................................................16
2.2Basic Program/Erase Mechanisms..........................................17
2.2.1 Energy band diagram during program and erase operation……........................................17
2.2.2 Carrier injection mechanisms.........................................19
2.3 Basic Reliability of Nonvolatile Memory....................................................25
2.3.1Retention………………………………………………....25
2.3.2Endurance………………………………………..............26
2.4Basic Physical Characteristic of Nanocrystal NVM.......................27
2.4.1 Quantum Confinement Effect………………………………......27
2.4.2 Coulomb Blockade Effect......................................................28
Chapter 3 Memory characteristics of CoSi2 nanocrystals memory device with Al2O3 as tunnel oxide.
3.1Motivation………………………………………………....39
3.2CoSi2 nanocrystals memory device with Al2O3 as tunnel oxide.................40
3.2.1Experimental Procedures…...............................40
3.2.2Results and Discussions…………………………………………...41
3.2.3 Summary I……………………………….............43
Chapter 4 Memory characteristics of CoSi2 nanocrystals memory device with high-k structure as tunnel oxide.
4.1.Motivation...................................................................................................50
4.2.CoSi2 nanocrystals memory device with HfO2/Al2O3/HfO2 as tunnel oxide..................................50
4.2.1Experimental Procedures.......................................50
4.2.2Results and Discussion.........................................52
4.2.3Summary II.................................................................53
4.3.CoSi2 nanocrystals memory device with Al2O3/HfO2/Al2O3as tunnel oxide.................................54
4.3.1 Experimental Procedures......................................54
4.3.2 Results and Discussion........................................54
4.3.3 Summary III...............................................................56
Chapter 5 Conclusion
5.1Conclusions.................................................................66

References.........................................................................68

References

Chapter 1

[1.1] S. Lai, Future Trends of Nonvolatile Memory Technology, December 2001.
[1.2] S. Aritome, IEEE IEDM Tech. Dig., 2000, p.763.
[1.3] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells—An overview” Proc. IEEE, vol. 85, pp. 1248–1271, Aug. 1997.
[1.4] Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti, “Introduction to Flash Memory” Proc. IEEE, vol. 91, NO.4, April 2003.
[1.5] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, 46, 1288 (1967).
[1.6] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, 1, 72 (2002).
[1.7] M. H. White, Y. Yang, A. Purwar, and M. L. French, ”A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Int’l Nonvolatile Memory Technology Conference, 52 (1996).
[1.8] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS,” IEEE circuits & devices, 16, 22 (2000).
[1.9] H. E. Maes, J. Witters, and G. Groeseneken, Proc. 17 European Solid State Devices Res. Conf. Bologna 1987, 157 (1988).
[1.10] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[1.11] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., 18, 278 (1997).
[1.12] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[1.13] H.A.R. Wegener, A.J. Lincoln, H.C. Pao, M.R. O’Connell, and R.E. Oleksiak, The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” IEEE IEDM Tech. Dig., Washington, D.C., 1967.
[1.14] T.Y.Chan, K.K.Young and C.Hu, “A true single-transistor oxide- nitride-oxide EEPROM device”. IEEE Electron Device Letters, vol.8, no.3, pp.93-95, 1987.
[1.15] M.K. Cho and D.M.Kim, “High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology”, IEEE Electron Device Letters, pp.399-401, Vol.21, No.8, 2000.
[1.16] I. Fijiwara, H.Aozasa, K.Nomoto, S.Tanaka and T.Kobayashi, “ High speed program/erase sub 100nm MONOS memory cell”, Proc. 18th Non-Volatile Semiconductor Memory Workshop, p. 75, 2001.
[1.17] H. Reisinger, M. Franosch, B. Hasler, and T. Bohm, Symp. on VLSI Tech. Dig. ,
9A-2, 113 (1997).
[1.18] C. Tung-Sheng, W. Kuo-Hong, C. Hsien, and K. Chi-Hsing, “Performance improvement of SONOS memory by bandgap engineering of charge-trappinglayer”, IEEE Electron Device Lett., vol. 25, no. 3, pp.205–207, Mar. 2004.
[1.19] Y. N. Tan, W. K. Chim, and B. J. Cho, W. K. Choi, “Over-Erase Phenomenon in SONOS-Type Flash Memory and its Minimization Using a Hafnium Oxide Charge Storage Layer”, IEEE Transations on Eelectron Devices, vol.51, no.7, July 2004.
[1.20] Min She, Hideki Takeuchi, and Tsu-Jae King, “Silicon-Nitride as a Tunnel Dielectric for Improved SONOS-Type Flash Memory”, IEEE Electron Device Letters, vol. 24, no. 5, MAY 2003.
[1.21] Chang-Hyun Lee, Kyu-Charn Park, and Kinam Kim, “Charge-trapping memory cell of SiO2/SiN/high-k dielectric Al2O3 with TaN metal gate for suppressing backward-tunneling effect”, Applied Physics Letters 87, 073510 (2005)
[1.22] Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, and Ping-Hung Yeh, “Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels”, Applied Physics Letters 90, 122111 (2007)
[1.23] Peiqi Xuan, Min She, Bruce Harteneck, Alex Liddle, Jefkey Bokor, and Tsu-Jae King, “FinFET SONOS Flash Memory for Embedded Applications”, IEEE IEDM 609-612 (2003).
[1.24] Tzu-Hsuan Hsu, Hang Ting Lue, Ya-Chin King, Jung-Yu Hsieh, Erh-Kun Lai, Kuang-Yeu Hsieh, and Chih-Yuan Lu, “A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for NAND-Type Flash Memory”, IEEE Electron Device Letters, vol. 28, no. 5, MAY 2007.
[1.25] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and Doug Buchanan, IEDM Tech. Dig., p.521 (1995)
[1.26] J De Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Trans. Nanotechnol, 2002.
[1.27] R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi, IEEE Trans. Electron Devices 49, 1392 (2002).
[1.28] Y. C. King, T. J. King, and C. Hu, IEEE Trans. Electron Devices 48, 696 (2001)
[1.29] Y. Shi et al., in Proceedings of the First Joint Symposium on Opto- and Microelectronic Devices and Circuits, 2000, pp. 142–145.
[1.30] H. G. Yang, Y. Shi, S. L. Gu, B. Shen, P. Han, R. Zhang, and Y. D. Zhang, Microelectron. J. 34, 71 (2003).
[1.31] Zengtao Liu, Chungho Lee, Venkat Narayanan, Gen Pei, and Edwin Chihchuan Kan, “Metal Nanocrystal Memories—Part I: Device Design and Fabrication”, IEEE Trans. Electron Devices, VOL. 49, NO. 9, SEPTEMBER 2002.
[1.32] Chungho Lee, Udayan Ganguly, Venkat Narayanan, and Tuo-Hung Hou, “Asymmetric Electric Field Enhancement in Nanocrystal Memories”, IEEE Eelectron Electron Letters, vol. 26, NO. 12, DECEMBER 2005.
[1.33] Jong Jin Leea, Yoshinao Harada Jung, Woo Pyun, and Dim-Lee Kwong “Nickel nanocrystal formation on HfO2 dielectric for nonvolatile memory device applications”, Applied Physics Letters 86, 103505 (2005)
[1.34] Wei-Ren Chen, Ting-Chang Chang, Po-Tsun Liu, Po-Sun Lin, Chun-Hao Tu, and Chun-Yen Chang “Formation of stacked Ni silicide nanocrystals for nonvolatile memory application”, Applied Physics Letters 90, 112108 (2007)
[1.35] S. K. Samanta, Won Jong Yoo, and Ganesh Samudra, “Tungsten nanocrystals embedded in high-k materials for memory application”, Applied Physics Letters 87, 113110 (2005)
[1.36] S. K. Samanta, P. K. Singh, Won Jong Yoo, Ganesh Samudra, and Yee-Chia Yeo, “Enhancement of Memory Window in Short Channel Non-Volatile Memory Devices Using Double Layer Tungsten Nanocrystals”, IEEE (2005)
[1.37] Shan Tang, Chuanbin Mao, Yueran Liu, and Sanjay K. Banerjee “Protein-Mediated Nanocrystal Assembly for Flash Memory Fabrication”, IEEE Trans. on Electron Letters, vol. 54, no. 3, March 2007.
[1.38] L. Guo, E. Leobandung, and S. Y. Chou, “Si single-electron MOS memory with nanoscale floating-gate and narrow channel,” in Int. Electron Devices Meeting Tech. Dig., 1996, pp. 955–956.
[1.39] N. Takahashi, H. Ishikuro, and T. Hiramoto, “A directional current switch using silicon electron transistors controlled by charge injection into silicon nano-crystal floating dots,” in Int. Electron Devices Meeting Tech. Dig., 1999, pp. 371–374.
[1.40] J. Wahl, H. Silva, A. Gokirmak, A. Kumar, J. J. Welser, and S. Tiwari, “Write, erase and storage times in nanocrystal memories and the role of interface states,” in Int. Electron Devices Meeting Tech. Dig., 1999, pp. 375–378.
Chapter 2
[2.1] Chih-Yuan and Chin-Chieh Yeh, “Advenced Non-Volatile Memory Devices with Nano-Technology”, Invited Talk for 15th International Conference on Ion Implantation Technology, 2004.
[2.2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, 85, 1248 (1997)
[2.3] M. Woods, Nonvolatile Semiconductor Memories: Technologies, Design, and Application, C. Hu, Ed. New York: IEEE Press, (1991) ch. 3, p.59.
[2.4] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika and S. Satoh, “Device characteristics of 0.35 μm P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming”, IEEE Trans. Electron Devices, Vol. 46, pp. 1866-1871, 1999.
[2.5] J. Bu, M. H. White, Solid-State Electronics., 45, 113 (2001)
[2.6] M. L. French, M. H. White., Solid-State Electron., p.1913 (1995)
[2.7] M. L. French, C. Y. Chen, H. Sathianathan, M. H. White., IEEE Trans CompPack and Manu Tech part A., 17, 390 (1994)
[2.8] Y. S. Hisamune, K. Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, A. Ishitani, and T. Okazawa, IEDM Tech. Dig., p.19 (1993)
[2.9] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Transactions of
Electron Devices., 49, 1606 (2002)
[2.10] J. Moll, Physics of Semiconductors. New York: McGraw-Hill, (1964)
[2.11] M. Lezlinger and E. H. Snow, J. Appl. Phys., 40, 278 (1969)
[2.12] Christer Sevensson and Ingemar Lundstrom, J. Appl. Phys., 44, 4657 (1973)
[2.13] P. E. Cottrell, R. R. Troutman, and T. H. Ning, IEEE J. Solid-State Circuits, 14, 442 (1979)
[2.14] C. Hu, IEDM Tech. Dig., p.22. (1979)
[2.15] S. Tam, P. K. Ko, C. Hu, and R. Muller, IEEE Trans. Elec. Dev., 29, 1740 (1982)
[2.16] I. C. Chen, C. Kaya, and J. Paterson, IEDM Tech. Dig., p.263 (1989)
[2.17] I. C Chen, D. J. Coleman, and C. W. Teng, IEEE Elec. Dev. Lett., 10, 297 (1989)
[2.18] T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka and H. Miyoshi, IEDM Tech. Dig., p.279 (1995)
[2.19] Suk-Kang Sung, I1-Han Park, Chang Ju Lee, Yong Kyu Lee, Jong Duk Lee, Byung-Gook Park, Soo Doo Chae, and Chung Woo Kim, ”Fabrication and Program/Erase Characteristics of 30-nm SONOS Nonvolatile Memory Devices, ” IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL.2, NO.4, DECEMBER 2003.
[2.20] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, 85, 1248 (1997)
[2.21] D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, “Statistical model ofreliability and scaling projections for Flash memories,” in IEDM Tech. Dig., 2001, pp.32.2.1–32.2.4.
[2.22] D. Ielmini, A. S. Spinelli, A. L. Lacaita, L. Confalonieri, and A. Visconti,“New
technique for fast characterization of SILC distribution in Flash arrays,” in Proc. IRPS, 2001, pp. 73–80.
[2.23] D. Ielmini, A. S. Spinelli, A. L. Lacaita, R. Leone, and A. Visconti, “Localization of SILC in Flash memories after program/erase cycling,” in Proc. IRPS, 2002, pp. 1–6.
[2.24] Y. M. Niquet, G. Allan, C. Delerue and M. Lannoo, “Quantum confinement in germanium nanocrystals,” Applied Physics Letters, vol.77, pp.1182-1184 (2000)
[2.25] T. Takagahara and K.Takeda, “Theory of the quantum confinement effect on excitons in quantum dots of indirect- gap materials,” Phys. Rev. B, Vol. 46, p. 15578, 1992.
[2.26] J.D.Jackson, “Classcial Electrodynamics”, published by John Wiley & Sons, 1999.
Chapter 3
[3.1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, Proceedings of the IEEE 91, 4 (2003).
[3.2] J. D. Blauwe, IEEE Trans. Nanotechnol. 1, 72 (2002).
[3.3] C. Y. Lu, T. C. Lu, and R. Liu, Proceedings of 13th IPFA (2006).
[3.4] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, IEDM Tech. Dig. 521 (1995).
[3.5] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron Devices. 49, 9 (2002).
[3.6] S. K. Samanta, W. J. Yoo, G. Samudra, E. S. Tok, L. K. Bera, and N. Balasubramanian, Appl. Phys. Lett. 87, 113110 (2005).
[3.7] T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze, Electrochem. Solid-State Lett. 8 (3) G71-G73 (2005).
[3.8] J. J. Lee, Y. Harada, J. W. Pyun, and D. L. Kwong, Appl. Phys. Lett. 86, 103505 (2005).
[3.9] C. C. Wang, J. Y. Tseng, T. B. Wu, L. J. Wu, C. S. Liang, and J. M. Wu, J. Appl. Phys. 99, 026102 (2006).
[3.10]Ch. Sargentis, K. Giannakopoulos, A. Travlos, and D. Tsamakis, Journal of Physics: Conference Series 10, 53-56 (2005).
[3.11] D. Zhao, Y. Zhu, R. Li, and J. Liu, Solid-State Electronics. 50, 2 (2006).
[3.12] R.E. dos Santos, I. Doi, J.A. Diniz; J.W. Swart, S.G. dos Santos Filho, “Investigation of Ni silicides formation on (100) Si by X-ray Diffraction (XRD)”, Revista Brasileira de Aplicacoes de Vacuo, v. 23, n. 1, 32-35, 2004.
Chapter 4
[4.1] S. Lai, “Tunnel oxide and ETOXTM flash scaling limitation,” 1998 Int'l Non-Volatile Memory Technology Conference, pp. 6-7, 1998.
[4.2] Jongwan Jung* and Won-Ju Cho**, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.8, NO.1, MARCH, 32-39 2008
[4.3] M. Specht, M. Städele, and F. Hofmann, “Simulation of high-K tunnel barriers for nonvolatile floating gate memories,” Proc. ESSDERC Conference, pp. 599-602, 2002.