近年來，非揮發性記憶體(NVM)在元件尺寸持續微縮下的需求為高密度記憶單元、低功率損耗、快速讀寫操作、以及良好的可靠度(Reliability)。傳統的浮停閘(floating gate)非揮發性記憶體在操作過程中如果產生漏電途徑，將會造成所有儲存的電荷流失，所以在資料儲存持久性(Retention)及耐操度(Endurance)的考量下，無法去微縮穿隧氧化層的厚度，故傳統的浮停閘非揮發性記憶體在元件尺寸小於五十奈米即遇到設計上的瓶頸。而奈米點記憶體被提出有希望可取代傳統浮停閘記憶體，由於奈米點記憶體中是由獨立分離的奈米點來儲存電荷，電荷對氧化層局部缺陷流失較不影響，所以可以在不損失可靠性的前提下，減少穿隧氧化層的厚度，進而降低操作電壓，操作速度增快，並使原件縮小，密度提高。
而選用金屬奈米點有以下幾個優點勝過其他材料，對通道層有更強的耦合能力、在費米能階附近有更高的能態密度、更大範圍可利用的功函數，使金屬奈米點非揮發性記憶體在半導體工業上有可能實際生產。
本篇論文旨在敘述，沉積矽化鈷當儲存層時同時通入氨氣、氮氣沉積，藉此用來形成鈷矽氮化物(Co-Si-N)，並應用於非揮發性奈米點記憶體中。室溫下在氬氣和氨氣(Ar/NH3)或是室溫下在氬氣和氮氣(Ar/N2)的環境下濺鍍混合靶材CoSi2藉此來形成鈷矽氮化物(Co-Si-N)，並且再經過氧氣環境下高溫700℃熱退火，使其在穿隧氧化層的上方析出奈米點。從電性量測結果也發現鈷奈米點元件的記憶體特性必須在製程700℃/ 60秒以上才會被觀察到，同時也發現在高密度的鈷矽氮化物奈米點被包覆在氮化矽(SiNX)中，有更好的資料儲存持久(Retention)。

Current requirement of nonvolatile memory (NVM) are high density cell, low-power wastage, high speed operation, and good reliability for the scaling down device. In a conventional nonvolatile memory, once the tunnel oxide develops a leaky path under repeated write/erase operation, all the stored charge will be lost. Therefore, the tunnel oxide thickness is incapable to scale down in terms of charge retention and endurance characteristics. Therefore conventional floating gate (FG) nonvolatile memories (NVMs) present critical issues on device scalability beyond the sub-50nm node. The nonvolatile nanocrystal memories are one of promising candidates to substitute for the conventional floating gate (FG) memories, because the nanocrystal memories storage charge by separated node. So it is not major influence of charge lost from partial oxide layer. The thickness of tunnel oxide can be reduce also can maintain good retention, therefore it is key to lowering operating voltages and increasing operating speeds. Also reduce device to increasing the density of device.
The advantages of metal nano-dot compared with other material counterparts include stronger coupling with the conduction channel, a wide range of available work functions, and higher density of states around the Fermi level. Because these advantages. It is possibility of metal nanocrystals nonvolatile memory fabricated in industry in practice.
In this thesis, an ease and low temperature fabrication technique of Co-Si-N nanocrystals was demonstrated for the application of nonvolatile memory. The nonvolatile memory structure of Co-Si-N nanocrystals embedded in the SiOx layer was fabricated by sputtering a co-mix target (CoSi2) in an Ar/N2 environment at room temperature. It can be considered that the nitrogen plays a critical role during sputter process for the formation of nanocrystal. In addition, the high density (~1012 cm-2) nanocrystal can be simple and uniform to be fabricated in our study. We also proposed a formation of Co-Si-N nanocrystals by sputtering a co-mix target (CoSi2) in the Ar/NH3 environment at room temperature. It was also found that high density Ni-Si-N nanocrystals embedded in the silicon nitride (SiNx) and larger memory effect.
A rapid thermal annealing (RTA) with process temperature at 700°C、800°C and short duration (60sec) was used to form nanocrystals. The charge storage layer of nanorystals embedded in SiNx shows larger memory window and better reliability over nanocrystals embedded in SiOx, due to different distributions of electronic field .

Chinese Abstract……………………………………………………….Ⅰ
English Abstract………………………………………………………..Ⅲ
Acknowledgement...................................................................................Ⅴ
Contents………………………………………………...………………ⅥFigure Captions………………………………………………………. Ⅸ
Chapter 1 Introduction
1.1 General Background ………...……………………………………………..1
1.2 SONOS nonvolatile memory device……………………………………….3
1.3 Nanocrystal nonvolatile memory device………………………………….4
1.4 Organization of this thesis………………………………………………...6
Chapter 2 Basic Principle of Nonvolatile Memory
2.1 Introduction.................................................................................................10
2.2 Basic Program/Erase Mechanisms..............................................................11
2.2.1 Energy band diagram during program and erase operation……..….11
2.2.2 Carrier injection mechanisms……………………………………….12
2.3 Basic Reliability of Nonvolatile Memory...................................................17
2.3.1 Retention…………………………………………………………....17
2.3.2 Endurance……………………………………………………….......18
2.4 Basic Physical Characteristic of Nanocrystal NVM...................................19
2.4.1 Quantum Confinement Effect……………………………………....19
2.4.2 Coulomb Blockade Effect…………………………………………..19
Chapter 3 Multi-Layer Co Silicide nanocrystal memory
3.1 Motivation………………………………………………………………...31
3.2 Experimental Procedures............................................................................32
3.3 Result and Discussion............................... ….............................................32
3.4 Summary I ………………………………………………………………..33
Chapter 4 Formation and nonvolatile memory effect of Co-Si-N
4.1. Motivation...................................................................................................41
4.2. Nonvolatile Co-Si-N nanocrystal memory by NH3……………………....43
4.2.1 Experimental Procedures………………………………...………….43
4.2.2 Results and Discussion………………………………………………44
4.3. Nonvolatile Co-Si-N nanocrystal memory by N2……………..………….46
4.3.1 Experimental Procedures……………………………………………46
4.3.2 Results and Discussion………………………………………………47
4.4. Summary II..................................................................................................49
Chapter 5 Conclusion
5.1 Conclusion………………………………………………………………...64

References................................................................................................66

Chapter 1
[1.1] S. Lai, Future Trends of Nonvolatile Memory Technology, December 2001.
[1.2] S. Aritome, IEEE IEDM Tech. Dig., 2000, p.763.
[1.3] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells—An overview” Proc. IEEE, vol. 85, pp. 1248–1271, Aug. 1997.
[1.4] Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti, “Introduction to Flash Memory” Proc. IEEE, vol. 91, NO.4, April 2003.
[1.5] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, 46, 1288 (1967).
[1.6] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, 1, 72 (2002).
[1.7] M. H. White, Y. Yang, A. Purwar, and M. L. French, ”A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Int’l Nonvolatile Memory Technology Conference, 52 (1996).
[1.8] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS,” IEEE circuits & devices, 16, 22 (2000).
[1.9] H. E. Maes, J. Witters, and G. Groeseneken, Proc. 17 European Solid State Devices Res. Conf. Bologna 1987, 157 (1988).
[1.10] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., 521 (1995).
[1.11] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., 18, 278 (1997).
[1.12] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., 115 (1998).
[1.13] H.A.R. Wegener, A.J. Lincoln, H.C. Pao, M.R. O’Connell, and R.E. Oleksiak, The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” IEEE IEDM Tech. Dig., Washington, D.C., 1967.
[1.14] H. Reisinger, M. Franosch, B. Hasler, and T. Bohm, Symp. on VLSI Tech. Dig. , 9A-2, 113 (1997).
[1.15] Tzu-Hsuan Hsu, Hang Ting Lue, Ya-Chin King, Jung-Yu Hsieh, Erh-Kun Lai, Kuang-Yeu Hsieh, and Chih-Yuan Lu, “A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for NAND-Type Flash Memory”, IEEE Electron Device Letters, vol. 28, no. 5 (2007)
[1.16] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and Doug Buchanan, “A Scalable Low Power Vertical Memory”, IEDM Tech. Dig., p.521 (1995)

Chapter 2
[2.1] Chih-Yuan and Chin-Chieh Yeh, “Advenced Non-Volatile Memory Devices with Nano-Technology”, Invited Talk for 15th International Conference on Ion Implantation Technology, 2004.
[2.2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, 85, 1248 (1997)
[2.3] M. Woods, Nonvolatile Semiconductor Memories: Technologies, Design, and Application, C. Hu, Ed. New York: IEEE Press, (1991) ch. 3, p.59.
[2.4] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika and S. Satoh, “Device characteristics of 0.35 m P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming”, IEEE Trans. Electron Devices, Vol. 46, pp. 1866-1871, 1999.
[2.5] J. Bu, M. H. White, Solid-State Electronics., 45, 113 (2001)
[2.6] M. L. French, M. H. White., Solid-State Electron., p.1913 (1995)
[2.7] M. L. French, C. Y. Chen, H. Sathianathan, M. H. White., IEEE Trans Comp Pack and Manu Tech part A., 17, 390 (1994)
[2.8] Y. S. Hisamune, K. Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, A. Ishitani, and T. Okazawa, IEDM Tech. Dig., p.19 (1993)
[2.9] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Transactions of Electron Devices., 49, 1606 (2002)
[2.10] J. Moll, Physics of Semiconductors. New York: McGraw-Hill, (1964)
[2.11] M. Lezlinger and E. H. Snow, J. Appl. Phys., 40, 278 (1969)
[2.12] Christer Sevensson and Ingemar Lundstrom, J. Appl. Phys., 44, 4657 (1973)
[2.13] P. E. Cottrell, R. R. Troutman, and T. H. Ning, IEEE J. Solid-State Circuits, 14, 442 (1979)
[2.14] C. Hu, IEDM Tech. Dig., p.22. (1979)
[2.15] S. Tam, P. K. Ko, C. Hu, and R. Muller, IEEE Trans. Elec. Dev., 29, 1740 (1982)
[2.16] I. C. Chen, C. Kaya, and J. Paterson, IEDM Tech. Dig., p.263 (1989)
[2.17] I. C Chen, D. J. Coleman, and C. W. Teng, IEEE Elec. Dev. Lett., 10, 297 (1989)
[2.18] T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka and H. Miyoshi, IEDM Tech. Dig., p.279 (1995)
[2.19] Suk-Kang Sung, I1-Han Park, Chang Ju Lee, Yong Kyu Lee, Jong Duk Lee,Byung-Gook Park, Soo Doo Chae, and Chung Woo Kim, ”Fabrication and Program/Erase Characteristics of 30-nm SONOS Nonvolatile Memory Devices, ” IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL.2, NO.4, DECEMBER 2003.
[2.20] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, 85, 1248 (1997)
[2.21] D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, “Statistical model of reliability and scaling projections for Flash memories,” in IEDM Tech. Dig., 2001, pp.32.2.1–32.2.4.
[2.22] D. Ielmini, A. S. Spinelli, A. L. Lacaita, L. Confalonieri, and A. Visconti,“New technique for fast characterization of SILC distribution in Flash arrays,” in Proc. IRPS, 2001, pp. 73–80.
[2.23] D. Ielmini, A. S. Spinelli, A. L. Lacaita, R. Leone, and A. Visconti, “Localization of SILC in Flash memories after program/erase cycling,” in Proc. IRPS, 2002, pp. 1–6.
[2.24] Y. M. Niquet, G. Allan, C. Delerue and M. Lannoo, “Quantum confinement in germanium nanocrystals,” Applied Physics Letters, vol.77, pp.1182-1184 (2000)
[2.25] T. Takagahara and K.Takeda, “Theory of the quantum confinement effect on excitons in quantum dots of indirect- gap materials,” Phys. Rev. B, Vol. 46, p.15578, 1992.
[2.26] J.D.Jackson, “Classcial Electrodynamics”, published by John Wiley & Sons, 1999.
Chapter 3
[3.1] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage,” in IEDM Tech. Dig., pp. 521--524, 1995.
[3.2] J. H. Chen, Y. Q. Wang, W. J. Yoo, Y.-C. Yeo, G. Samudra. D. S. H. Chan, A. Y. Du, and D.-L. Kwong, “Nonvolatile flash memory device using Ge nanocrystals embedded in HfAlO high-k tunneling and control oxides: Device fabrication and electrical performance” ” IEEE Trans. Electron Devices, vol. 51, pp. 1840 - 1848, Nov. 2004.
[3.3] J. D. Blauwe, “Nanocrystal Nonvolatile Memory Devices” ” IEEE Trans. on nanotechnology, vol.. 1, pp. 72-77, March. 2002.
[3.4] C. Lee, A. G. Seetharam and E. C. Kan, “Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Singleand Double-Layer Metal Nanocrystals,” in IEDM Tech. Dig., pp.22.6.1-- 22.6.4, 2003.
[3.5] Enhancement of Memory Window in Short Channel Non-Volatile Memory Devices Using Double Layer Tungsten NanocrystalsS. K. Samanta1, P. K. Singh1, Won Jong Yoo1, Ganesh Samudra1,Yee-Chia Yeo1, L. K. Bera, and N.
Balasubramanian IEEE (2005)
[3.6] R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi, in IEDM Tech. Dig., pp. 313-316, 2000.
Chapter 4
[4.1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, Proceedings of the IEEE 91, 4 (2003).
[4.2] J. D. Blauwe, IEEE Trans. Nanotechnol. 1, 72 (2002).
[4.3] C. Y. Lu, T. C. Lu, and R. Liu, Proceedings of 13th IPFA (2006).
[4.4] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, IEDM Tech. Dig. 521 (1995).
[4.5] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron Devices. 49, 9 (2002).
[4.6] S. K. Samanta, W. J. Yoo, G. Samudra, E. S. Tok, L. K. Bera, and N. Balasubramanian, Appl. Phys. Lett. 87, 113110 (2005).
[4.7] T. C. Chang, P. T. Liu, S. T. Yan, and S. M. Sze, Electrochem. Solid-State Lett. 8(3) G71-G73 (2005).
[4.8] J. J. Lee, Y. Harada, J. W. Pyun, and D. L. Kwong, Appl. Phys. Lett. 86, 103505 (2005).
[4.9] C. C. Wang, J. Y. Tseng, T. B. Wu, L. J. Wu, C. S. Liang, and J. M. Wu, J. Appl. Phys. 99, 026102 (2006).
[4.10]Ch. Sargentis, K. Giannakopoulos, A. Travlos, and D. Tsamakis, Journal of Physics: Conference Series 10, 53-56 (2005).
[4.11] D. Zhao, Y. Zhu, R. Li, and J. Liu, Solid-State Electronics. 50, 2 (2006).
[4.12] P. H. Yeh, C. H. Yu, and L. J. Chen, H. H. Wu, P. T. Liu, and T. C. Chang, Appl. Phys. Lett 87, 193504 (2005).
[4.13] C. Lee, T. H. Hou, and E. C. Kan, IEEE Trans. Electron Devices 52, 12 (2005)
[4.14] C. Lee, T. H. Hou, and E. C. Kan, IEEE Trans. Electron Devices 52, 12 (2005)
[4.15] JooHyung Kim, JungYup Yang, JunSeok Lee, and JinPyo Hong. Appl. Phys. Lett. 92, 013512 (2008)
[4.16] C. W. J. Beenakker, Phys. Rev. B 44, 1646 (1991).