電力線通訊是一種利用電力線來做為傳輸媒介的通訊技術，目前PLC技術正在快速成長的階段，逐漸打入各類應用市場，其中包括智慧電網、照明控制、能源計量儀表、住宅視訊傳送以及電動車。透過電力線傳輸訊號過程中，容易受到環境因素的影響，造成傳輸資料錯誤，而降低了對電力線通訊的使用，為了保證資料的正確性、完整性、安全性，本論文設計出具高偵錯、糾錯能力和加解密之調變/解調電力線通訊晶片。
本論文目的藉由晶片實現將訊號透過電力線做半雙工傳輸，運用CRC-16確定資料的正確性。計算BCH code能對資料做3位元的錯誤糾正。使用TEA加密演算法對64位元的資料做加解密處理。利用Interleaving技術將Burst error轉變成 random error。透過PWM對輸入訊號做調變使訊號轉換成不同頻率方波。利用FSK技術作頻率調變，轉換成數位訊息。本晶片設計採用TSMC 0.18μm製程，為全數位電路設計，並應用於能源電表管理。

Power Line Communications (PLC) is a used of power lines as a transmission medium of communication technology. Currently PLC technology is growing and maturing rapidly, and gradually into the market of applications, including smart grid, lighting control, energy measurement instruments, video delivery, and electric car. Power line transmission signal is susceptible to the environmental factors which cause data errors in the power line transmission, the main reason of the low utilization of PLC. In order to guarantee the correctness, completeness, security, the thesis issued by high design debug, error correction capability and encryption/decryption modulation/demodulation power line communications chips.
The purpose of this thesis is to design chips to make the signal half-duplex transmission through power lines. CRC-16 is used to determine the data accuracy. BCH code is calculated to perform the 3-bit error correction. TEA encryption algorithm is implemented for 64-bit data encryption and decryption. By using Interleaving technology burst error into random error. The PWM modulated the input signal so that signal turns into different square wave frequency. FSK is used for frequency demodulation. It can convert pulses into digital information. The chip design using TSMC 0.18μm process is fully digital circuit and is applied for the electric meter management.

CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Research Objective and Contribution 2
1.3 Thesis Organization 4
CHAPTER 2 THE COMMUNICATION TECHNIQUES OF PLC 5
2.1 PLC Circuit Structure 5
2.2 Transmit Protocol 6
2.2.1 PLC Transmitting Theory 6
2.2.2 Universal Asynchronous Receiver/Transmitter (UART) 7
2.3 Signal Modulation 8
2.3.1 Digital Signal Modulation 8
2.3.2 Pulse Width Modulation 10
CHAPTER 3 BASEBAND DESIGN 12
3.1 Cyclic Redundancy Check (CRC) 12
3.1.1 CRC theory 12
3.1.2 CRC Generator 13
3.1.3 CRC Deceiver 16
3.2 Interleaving Technique 17
3.2.1 Interleaving Technique 17
3.2.2 Interleaving Circuit Design 19
3.2.3 Deinterleaver 20
3.3 Tiny Encryption Algorithm 21
3.3.1 TEA Theory 21
3.3.2 TEA Encoder 23
3.3.3 TEA Decoder 25
3.4 Modulator 26
3.4.1 Digital FSK Modulator 26
3.4.2 Digital FSK Demodulator 28
CHAPTER 4 BINARY BCH ENCODER/DECODER 33
4.1 Binary BCH Overview 33
4.2 BCH Encoder 35
4.3 BCH Decoder 37
4.3.1 Basic Concept 37
4.3.2 Computing Syndrome Module 39
4.3.3 Finding Error Pattern Module 41
4.3.4 Error Correcting Module 43
CHAPTER 5 PCB BOARD DESCRIPTION 45
5.1 Powerline Transceiver Description 45
5.2 Coupling Interface 45
5.2.1 Transmitting section 46
5.2.2 Receiving section 48
CHAPTER 6 MEASUREMENT RESULT 50
6.1 Verification Flow 50
6.2 Simulation Result 51
6.3 Measurement Result 54
6.4 PLC Test 56
6.5 Chip Specification 58
CHAPTER 7 CONCLUSION AND FUTURE WORK 59
7.1 Conclusion 59
7.2 Future Work 59
Reference 60

[1] 李淑敏、郭可驥、王朝欽與陳朝順，「節能通信 IC 晶片開發與智慧型電能管理系統整合研究」，NSC98-2220-E-110-009，2008。
[2] Jia-Wi Guo, “A modulation/demodulation chip design with error correctable and high error detected ability for Power Line Communication,” Department of Computer Science and Engineering, National Sun Yat-sen University, Master Thesis, 2011.
[3] Shouqian Yu, Lili Yi, Weihai Chen and Zhaojin Wen, “Implementation of a Multi-channel UART controller Based on FIFO Technique and FPGA”, Industrial Electronics and Applications, 2007. ICIEA 2007. 2nd IEEE Conference on, pp, 2633-2638, 2007.
[4] J. Machacek and J. Drapela, “Control of serial port (RS232) communication in LabVIEW,” International Conference on ModemTechnique and Technologies, pp. 36-40, 2001.
[5] 劉建邦，「基於OSC-ANF之PLC系統的規劃及研究」，頁4-9，逢甲大學電機工程系碩士在職專班碩士論文，2007。
[6] 蔡恩民，「應用於身心障礙者之家庭自動化電力線網路系統之研製」，頁4-8，國立成功大學電機工程學系碩士在職班論文，2008。
[7] W. W. Peterson, and D. T. Brown, “Cyclic Codes for Error Detection”, Proceedings of the IRE 49, pp. 228, Jan. 1961.
[8] Dong-Ruei Tsai, “The Design and Implement of Digital Chip for Power Line Communication”, Department of Computer Science and Engineering, National Sun Yat-sen University, Master Thesis, 2012.
[9] S. Shukla, and N.W. Bergmann, “Single bit error correction implementation in CRC-16 on FPGA,” 2004 IEEE International Conference, pp. 319-322, 2004.
[10] William Stallings, “Wireless communications and network”, Prentice Hall, pp. 206-213, 2002.
[11] Roger M. Needham, and David J. Wheeler., “TEA, a tiny encryption algorithm,” Lecture Notes in Computer Science, Vol. 1008, pp. 363-366, 1994.
[12] 陳俊麟，「於Auto-ID的環境中使用加密傳輸」，頁15-24，國立交通大學資訊管理研究所碩士論文，2004。
[13] Vikram Reddy Andem, "A Cryptanalysis of the Tiny Encryption Algorithm," Master thesis, The University of Alabama, Tuscaloosa, 2003.
[14] A. Prodic, D. Maksimovic, and R. Ericson, “Design and implementation of a digital PWM controller for a high-frequency switching DC-DC power converters,” Proc. IEEE IECON Conf., pp. 331-362, 2002.
[15] M. Ghovanloo and K. Najafi, ”A high data transfer rate frequency shift keying demodulator chip for the wireless biomedical implants” IEEE Midwest Symposium on Circuits and Systems Proc,vol.3,pp. 433-436, Aug 2002.
[16] M. Ghovanloo and K. Najafi, ”A fully digital frequency shift keying demodulator chip for wireless biomedical implants” Southwest Symposium on Mixed Signal Design, pp.223-227, Apr 2003.
[17] S. Lin and D.J. Costello, “Error Control coding: Fundamentals and Applications” ,Prentice-Hall Inc., Englewood Cliffs, NJ, second edition, 2004.
[18] 徐誌宏，”Design of Reed-Solomon Decoder and Implement on FPGA”，國立雲林科技大學電子工程系, 碩士論文，2007。
[19] 陳德軒，“An Adaptive-Rate Error Correction Scheme for NAND Flash Memory”， 國立清華大學電機工程學系， 碩士論文，2008。
[20] Massey, J. L., “Step-by-Step Decoding of Bose-Chauhuri-Hocquenghem Codes,” IEEE Trans. Inform. Theory, Vol. 11, No. 4, pp. 580-585, Nov. 1965.
[21] Chr, C., Su, S. L. and Wu, S. W., “New Step-by-Step Decoding for Binary BCH Codes,” The Ninth International Conf. on Commun. Systems, pp. 456–460, 6-8 Sept. 2004.
[22] 林銀議，「數位通訊原理－編碼與消息理論」，頁117-168，台北：楊榮川，2005。
[23] C. L. Chr, S. L. Su, and S. W. Wu, “New step-by-step decoding for binary BCH codes”, The Ninth International Conference on Communications Systems, pp.456, Sep 2004.
[24] Laurie L. Joiner, and John J. Komo, “Decoding Binary BCH Codes,” IEEE Trans., 1995.
[25] A. Dur, “Avoiding decoder malfunction in the Peterson-Gorenstein-Zierler decoder,” IEEE Trans. Information Theory, Vol. 39, pp. 640-643, Mar 1993.
[26] M. Kuijper, “A system-theoretic derivation of the Welch-Berlekamp algorithm,” in Proc. 2000 IEEE Int. Symp. Information Theory, Sorrento, Italy, pp. 418, Jun 2000.
[27] Huapeng Wu, “Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis”, IEEE Transactions on Computers, Vol.51, No. 7, pp.750-758, Jul 2002.
[28] Shayan, Y.R., Le-Ngoc, T. and Bhargava, V.K., "A Binary-Decision Approach to Fast Chien Search for Software Decoding for BCH Codes", IEEE Proceedings, Part F, pp. 629-632, Oct 1987.