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博碩士論文 etd-0625113-165815 詳細資訊
Title page for etd-0625113-165815
論文名稱
Title
快速低功耗管線暨連續逼近式類比數位轉換器設計
A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
89
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-17
繳交日期
Date of Submission
2013-07-26
關鍵字
Keywords
類比數位轉換器、連續逼近式、管線式、管線暨連續逼近式類比數位轉換器、低功率
SAR, ADC, Low Power, Pipelined-SAR ADC, Pipelined, Analog-to-Digital Converter
統計
Statistics
本論文已被瀏覽 5750 次,被下載 76
The thesis/dissertation has been browsed 5750 times, has been downloaded 76 times.
中文摘要
本論文提出了一高速低功耗之管線式曁連續逼近式類比數位轉換器。將原本使用在管線式類比數位轉換器之子類比數位轉換器,快閃式類比數位轉換器,經由低功耗之逐次逼近式類比數位轉換器取代。採用管線式類比數位轉換器高速高解析,以及逐次逼近式類比數位轉換器低功耗之優點來達到高速低功耗的設計目標。
1. 採用兩階段的管線式架構,降低高功率消耗運算放大器的使用,並且利用逐次逼近式類比數位轉換器之電容陣列經由輸入取樣開關取代前端取樣保持電路的設計,使整個類比數位轉換器電路只需使用一個運算放大器。
2. 採用動態比較器以及非單調性電容陣列切換方法,降低整體電路功率消耗。
3. 設計一額外的比較器在電路取樣階段時進行最高有效位元之轉換,提高類比數位轉換器之轉換速度,並且可減輕管線式架構中運算放大器之設計難度。
4. 設計一結合兩種形式之電容陣列在第一級的逐次逼近式類比數位轉換器中使用,使之適用於管線式類比架構的應用,並且相較於傳統二進制電容陣列達到更低的功率消耗。
Abstract
A high speed and low power Pipelined-SAR ADC is proposed in this thesis. The Flash ADC which is often found in traditional Pipelined ADC is replaced by the energy efficient SAR ADC. By taking the advantages of the pipelined ADC with high speed and high resolution and the SAR ADC with low power consumption.
1. Using only two stages in the proposed ADC architecture, and reduce the requirement of power hungry operation amplifier. Removing the front-end sample-and-hold circuit by capacitor array in the SAR ADCs and sample switch. Hence, the whole circuit only requires one operation amplifier which uses in MDAC circuit.
2. The comparators in the proposed ADC are dynamic comparators which consume no static power consumption. Capacitor arrays used in the SAR ADC adopt the monotonic switching procedure to achieve energy efficient and high speed applications.
3. An additional comparator for MSB is designed for the ADC using in sample phase. It can enhance the sample rate of ADC and relax the design difficulty of the operation amplifier in MDAC.
4. A capacitor array combined two kinds of capacitor array is proposed for pipelined-SAR ADC application.
目次 Table of Contents
論文提要 II
致謝 III
中文摘要 IV
ABSTRACT V
CONTENTS VI
List of Figures VIII
List of Tables XI
Chapter 1 Introduction 1
1.1 Motivation 1
2.1 Thesis Organization 3
CHAPTER 2 Overview of Analog to Digital Converter 4
2.1 ADC Performance Specifications 4
2.2 ADC Architectures 11
2.2.1 Flash 11
2.2.2 Two-Step Flash ADC 12
2.2.3 Pipelined 13
2.2.4 Successive Approximation 15
2.2.5 Pipelined-SAR 17
CHAPTER 3 Design of Pipelined-SAR ADC 19
3.1 Introduction 19
3.2 Switch 19
3.2.1 ON-Resistance 19
3.2.2 Charge-Injection 20
3.2.3 Clock Feedthrough 21
3.3 Sample and Hold Circuit 22
3.4 Capacitor Array 25
3.4.1 Binary Weighted Capacitor Array 25
3.4.1 C-2C Capacitor Array 26
3.4.3 Binary Weighted Array with Monotonic Capacitor Switching 27
3.5 Comparator 28
3.5.1 Static Latched Comparator 29
3.5.2 Class-AB Latched Comparator 30
3.5.3 Dynamic Latched Comparator 31
3.6 Operation Amplifier 32
3.6.1 DC Gain 33
3.6.2 Bandwidth and Slew Rate 35
3.6.3 Output Impedance and Output Voltage Range 36
CHAPTER 4 Implementation of Pipelined-SAR ADC 38
4.1 Switch 38
4.1.1 Transmission Gate 39
4.1.2 Bootstrapped Switch 41
4.2 Dynamic Comparator 43
4.3 Additional Comparator for MSB 45
4.4 1st-Stage of Successive Approximation ADC 47
4.4.1 Capacitor Array and SAR Algorithm for Pipelined-SAR Application 50
4.4.2 DAC Logic 54
4.5 2nd-Stage of Successive Approximation ADC 55
4.5.1 Capacitor Array 59
4.5.3 DAC Logic 62
4.6 SAR Logic 63
4.7 MDAC 65
CHAPTER 5 Conclusion 71
References 73
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