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博碩士論文 etd-0625113-170420 詳細資訊
Title page for etd-0625113-170420
論文名稱
Title
使用統計型時序分析來規劃電源區域實現低功率IC設計採用90奈米製程
Low Power IC Design Using Statistical Static Timing Analysis to Programming Power Domains in 90nm CMOS Technology
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
81
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-17
繳交日期
Date of Submission
2013-07-25
關鍵字
Keywords
多重電壓源、靜態時序分析、關鍵路徑、統計型時序分析、電壓轉換器
Static Timing Analysis, Level Converter, Critical Path, Multiple-Supply Voltage
統計
Statistics
本論文已被瀏覽 5727 次,被下載 251
The thesis/dissertation has been browsed 5727 times, has been downloaded 251 times.
中文摘要
隨著半導體製程的發展,積體電路的功率消耗則有越來越高的趨勢,因此降低電路的消耗功率變成一個重要的議題,若無法有效的降低功率消耗,晶片之溫度將會過高而導致功能失效,為了保全晶片的正常工作以及延長電池的壽命,現行的晶片通常都是以降低供應電壓源來節省功率消耗;但是直接降低電壓源又會影響晶片的效能,而在降低IC的消耗功率且不影響IC效能的前提下,使用多重電壓源來設計晶片是一個直接且有效的方法。
隨著VLSI製程的快速縮小,製程解析度甚至比光學微影技術(optical lithography)所用的波長還小時,製造的控制誤差越來越無法精準的控制且即使在同一製造環境下不可避免的會有許多誤差呈相類似的統計分佈,並且會有許多相關性,因此使用靜態時序分析(Static Timing Analysis)找出的關鍵路徑(Critical Path) 可能不夠準確,為了克服這個問題。本論文提出了一個多電壓源晶片的設計方法,以設計的貪婪演算法對電路做電源配置,再使用統計型的時序分析(Statistical Timing Analysis; SSTA)之概念對電路做時序分析與驗證,找出電路中的Path會成為(Critical Path)的機率(Path Sensitivity),且使用Cell-Based的方式將自己設計的電壓轉換器(Level Converter)嵌入一般組合電路中,讓部分不需要較大供應電壓的元件使用恰當的電壓,以達到降低消耗功率的目的。
Abstract
With the improvement of semiconductor manufacturing processes, the power consumption of the integrated circuit(IC) is growing rapidly. Therefore, the power consumption reduction of IC is also becoming an important issue. If we cannot reduce the power consumption effectively such that it will cause the IC overheat and its functional failure. In order to preserving the normal operation and extend the battery life of the chips. Nowadays, the chips are usually saving the power consumption by reducing the supply voltage. However, it will affect the performance of the chips by reducing the supply voltage directly. Under the premise, there is a direct and effective method that it can reduce the power consumption and without affect the performance for designing the IC by the Multiple Supply Voltage architecture (MSV).
With the narrower line width in the VLSI processes, the processes resolution is smaller than the wavelength of Optical Lithography. Hence, the error control of the fabrication cannot accurate increasingly. Therefore, there are many similar statistical distributions of the errors emerged and present many relevant even in the same manufacturing environment. For the reason that using the Static Timing Analysis to identify the critical path could be inaccurate. In order to overcoming this problem, this thesis proposes a method to design the MSV chips which is using greedy algorithm to make voltage assignment on the IC. Then we use the Statistical Static Timing Analysis for analyzing and verifying the timing of circuit. It can search the Path Sensitivity which exactly equals to the probability of the path that is critical path. We embed the Level Converter that we designed into the combinational circuit by using Cell-Based manner and let some cells applying the appropriate lower supply voltage to substitute the higher supply voltage for achieving the purpose of reducing power consumption.
目次 Table of Contents
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Research Goals and Contribution 1
1.3 Thesis Organization 3
CHAPTER 2 Background Overview 4
2.1 Power Consumption of CMOS circuits 4
2.1.1 Power Consumption 4
2.1.2 Dynamic Power Consumption 4
2.1.3 Short Circuit Power Consumption 5
2.1.4 Leakage Power Consumption 6
2.2 Multiple-Supply Voltage Design 7
2.2.1 Clustered Voltage Scaling (CVS) 7
2.2.2 Extended Clustered Voltage Scaling 10
2.2.3 Dynamic Clustering 11
2.3 Summary 12
CHAPTER 3 Static Timing Analysis and Statistical Static Timing Analysis 14
3.1 Introduction of Timing Analysis 14
3.1.1 Modeling of CMOS 14
3.1.2 Information of Timing 15
3.1.3 Interconnect Delay 16
3.1.4 Propagation Delay 17
3.1.5 Transition Delay 18
3.2 Static Timing Analysis 19
3.2.1 Timing Arcs and Unateness 19
3.2.2 Operating Conditions 20
3.2.3 Lookup Table 21
3.2.4 Introduction of Static Timing Analysis 23
3.2.5 STA applied on MSV design 26
3.3 Statistical Static Timing Analysis 28
3.3.1 Introduction 28
3.3.2 Obtain Linear Model 29
3.3.3 Path Delay Distributions Based on Parameter Distributions 30
3.3.4 Perturbation and PDF (Probability Distribution 31
3.3.5 Path Sensitivity 32
CHAPTER 4 Algorithm and Design flow 36
4.1 Algorithm 36
4.1.1 Design Principles 36
4.1.2 Design Flow of Algorithm 37
4.1.3 Timing Analysis and Power Analysis 37
4.1.4 Voltage Assignment 40
4.1.5 Insert Level Converter 42
4.1.6 Timing Verification by SSTA 44
4.2 Design Flow 45
4.2.1 Standard Cell Flow 45
4.2.2 Construct Synopsys Library Model 46
4.3 Level Converter 50
4.3.1 Level Converter used in MSV 50
4.3.2 Conventional Level Shifter Circuit 51
4.3.3 Improvement Level Converter 53
4.3.4 Simulation of the Level Converter 54
4.4 Mixed level converter with TN90MSG Standard Cell to implement MSV 56
4.4.1 Design Flow 56
4.4.2 Place and Route Model 58
4.4.3 MSV implementation by SOC Encounter 59
CHAPTER 5 Simulation Results 60
5.1 Performance Comparison 60
CHAPTER 6 64
6.1 Conclusion 64
6.2 Future Works 64
Reference 65
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