本論文共分為兩個主題：第一部份為三維解碼架構之唯讀記憶體的說明與實作，第二部分為我們自己設計的網路介面控制器。

一、 唯讀記憶體解碼器之省面積架構

針對P型植入唯讀記憶體架構，提出一個新式之三維解碼方式來達到節省面積，及提高存取速度。且我們以全客戶設計方式，在聯電UMC 2P2M的製程下完成此晶片設計，目前下線生產中。

二、 網路介面設計控制器

此設計為網路卡介面之MAC層，負責接收及傳送由媒介獨立介面（Medium Independent Interface， MII之IEEE802.3）網路封包。我們已完成整個Network Interface Controller之規劃且gate level模擬亦已驗證無誤。

The thesis is composed of two different IC design projects, which are briefly introduced as follows.

The first topic is an area-saving decoder structure for ROMs. In this part of work, we propose a novel 3-dimensional decoding method. The stages of address decoding are drastically shortened. Hence, the delay is reduced as well as the power consumption. The overall transistor count and the delay are thoroughly derived. A physical 256x8 ROM using the proposed decoder is fabricated by UMC 0.5 mm 2P2M CMOS technology.

The second part is the NIC (Network Interface Controller) design. The NIC transfers data frames from and to transmitter and receiver buffers in the host memory, respectively. Meanwhile, the transferred data must also comply with the IEEE 802.3 standard. The design is compatible with CSMA/CD type Local Area Network, including 10/100 Mbps Ethernet.

摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表格目錄 ix
第一章 簡介 1
1.1 前言 1
1.2 論文目的 2
1.3 論文大綱 2
第二章 唯讀記憶體ROM解碼器之 省面積架構 3
2.1 研究動機 3
2.2 ROM原理簡介 5
2.2.1 金氧半型ROM記憶格陣列 5
2.3 解碼架構簡介 7
2.3.1 一維解碼架構 7
2.3.2 二維解碼架構 9
2.3.3 三維解碼架構 13
2.3.4 樹型解碼架構 16
2.4 效能評估 18
2.5 256x8 ROM省面積架構之晶片實作 24
2.5.1 電路設計 24
2.5.2 測試考量 27
2.5.3 腳位說明 29
2.5.4 模擬結果 29
2.5.5 晶片佈局圖 33
第三章 網路介面控制器 34
3.1 研究動機 34
3.2 原理說明 36
3.3 架構說明 39
3.3.1 RX 10/100 Mbps CSMA/CD 40
3.3.1.1 接收部份控制（Rx MAC）模組： 42
3.3.1.1.1 Rx start模組： 42
3.3.1.1.2 Packet Filter模組： 45
3.3.1.1.3 CRC模組： 47
3.3.1.1.4 Receive 模組： 50
3.3.1.1.5 Rx_leng模組： 52
3.3.1.2 Bus Arbiter模組： 54
3.3.1.3 Rx DMA和Rx Control模組： 56
3.3.2 TX 10/100 Mbps CSMA/CD 60
3.3.2.1傳送部份控制（Tx MAC）模組： 62
3.3.2.1.1 Transmit模組： 62
3.3.2.1.2 Backoff模組： 64
3.3.2.2 Bus Arbiter模組： 67
3.3.2.3 Tx DMA和Tx Control模組： 69
3.4 模擬結果 73
3.5 測試考量 81
3.6 晶片佈局圖 82
第四章 結論 83
參考文獻 84

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