Title page for etd-0626100-134230


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URN etd-0626100-134230
Author Ying-Pei Chen
Author's Email Address baby@vlsi.ee.nsysu.edu.tw
Statistics This thesis had been viewed 4746 times. Download 1237 times.
Department Electrical Engineering
Year 1999
Semester 2
Degree Master
Type of Document
Language zh-TW.Big5 Chinese
Title A Area-Saving ROM Decoder and Design of Network Interface Controller
Date of Defense 2000-06-06
Page Count 85
Keyword
  • Network Interface Controller
  • A Area-Saving ROM Decoder
  • Abstract The thesis is composed of two different IC design projects, which are briefly introduced as follows.
    The first topic is an area-saving decoder structure for ROMs. In this part of work, we propose a novel 3-dimensional decoding method. The stages of address decoding are drastically shortened. Hence, the delay is reduced as well as the power consumption. The overall transistor count and the delay are thoroughly derived. A physical 256x8 ROM using the proposed decoder is fabricated by UMC 0.5 mm 2P2M CMOS technology.
    The second part is the NIC (Network Interface Controller) design. The NIC transfers data frames from and to transmitter and receiver buffers in the host memory, respectively. Meanwhile, the transferred data must also comply with the IEEE 802.3 standard. The design is compatible with CSMA/CD type Local Area Network, including 10/100 Mbps Ethernet.
    Advisory Committee
  • Sying-Jyan Wang - co-chair
  • Ing-Jer Huang - co-chair
  • Chua-Chin Wang - co-chair
  • Files
  • 碩士論文.pdf
  • indicate access worldwide
    Date of Submission 2000-06-26

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