在使用分碼多工技術之展頻通訊系統中，展頻碼信號的同步有著非常重要的地位，也是接收端設備的重要工作之一，然而，在大部分的相關文獻中，都存在接收信號和傳送端發出之信號已達成同步的假設，使得接收機得以產生和發射端相同的信號來做進一步的信號處理與分析；另外，針對基本的展頻碼同步電路架構、機制之運作來作探討的相關文獻不多，因此，缺乏同步電路中，元件或模組的特性與運作模式之相關資訊，而無法以一個系統的角度，對展頻碼同步電路作深入的了解、運用與改良。因此，在本論文中即針對展頻碼信號的同步問題來做相關的研究。
一個展頻通訊接收系統必須透過獲取和追蹤的程序才能達到與傳送端的信號同步，在本論文中，藉由使用獲取搜尋技術取得所需的資訊，配合追蹤迴路及回授控制策略的運作，校正本地振盪器的時脈頻率，產生與接收信號匹配的本地展頻碼信號，進而達到同步的目的。
在本研究中，將針對展頻碼同步電路作電腦模擬，並針對其關鍵模組與整體架構作特性分析。在獲取程序方面，將採用串列式搜尋技術，並提出一些輔助判別法則加以搭配，來提昇同步系統的運作性能；在追蹤程序方面，則使用同調延遲鎖定追蹤迴路，並對基本特性與不同的系統參數、通道環境作進一步的模擬分析，藉由比較分析的結果，可進而在實作與改良展頻碼同步系統的時候作為參考、採用和判斷的依據。另外，則提出一個同調展頻碼追蹤迴路架構的晶片實作，並經由合成、驗證、佈局、以及最後的模擬驗證，完成下線前的所有設計流程。

PN code synchronization is a common and essential task at the receiver in CDMA communication systems. In most literatures, there usually exists assumption of synchronization between the received spreading sequence and a locally generated replica. Few practical and detail synchronization schemes are showed in literatures. Moreover, there are no sufficient knowledge about operation characteristics of loop elements and operation strategies. Hence, in this thesis we propose some schemes about PN code synchronization and then do some analysis to compare performance of those schemes in AWGN channel.
Code synchronization at DSSS receivers is performed in two steps. One is code acquisition and the other is code tracking. In acquisition process, we propose so called some “auxiliary decision criterions” in multiple-dwell detection strategies. Analytical results are validated with computer simulations. By use of auxiliary decision criterions, the acquisition process is outperforms the conventional multiple-dwell and single-dwell detection strategies in AWGN channel. In code tracking process, we use coherent DLL. Loop filter parameters are tuned by observing phase-plane trajectories to acquire stable lock points and convergence property. In addition, we proposed a coherent DLL chip implementation, and accomplish the design flow that includes verification, synthesis, place and route, and simulation.

誌謝 i
中文摘要 iii
英文摘要 iv
目錄 v
附圖目錄 vii
第一章 緒言 1
1.1 文獻探討 1
1.2 研究動機 4
第二章 展頻通訊系統中展頻碼同步程序的理論介紹與分析 6
2.1 展頻碼同步覆始程序之模型定義 7
2.2 展頻碼獲取迴路 12
2.2.1 串列式搜尋技術在可加性白色高斯雜訊下的訊號檢測 12
2.2.1.1 固定積分時間檢測法 13
2.2.1.2 多暫留時間檢測法 13
2.2.2 追蹤迴路的拉回 17
2.3 展頻碼追蹤迴路 18
2.4 電腦模擬與說明 23
2.4.1 展頻碼追蹤迴路的電腦模擬 25
2.4.2 結合展頻碼獲取和追蹤迴路的電腦模擬 36
第三章 展頻碼追蹤迴路之晶片設計實作 54
3.1 同調延遲鎖定迴路的晶片架構介紹 55
3.2 同調延遲鎖定迴路晶片之運作模擬結果 58
第四章 展頻碼同步程序的運作方案 66
4.1 判別門限的設定 67
4.2 搜尋/鎖定策略的架構 79
4.3 電腦模擬 86
第五章 結論與建議 97
參考文獻 99
索引 103

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