本論文共涵蓋兩個不同的主題：第一部份為使用雙門檻電壓之6-電晶體靜態記憶體及低功率止擾器的實作。本晶片設計之重點為使用雙門檻電壓電晶體的SRAM記憶單元，其優點為加快記憶體的存取速度同時維持資料的完整。並提出背對背止擾器 (Quenchers) 以消除記憶體在輸出資料線上大電流所造成的不必要之震盪現象。

第二部份為可程式化鎖相迴路式倍頻器，使用鎖相迴路的架構及可程式化除頻器來實現，可提供高速數位電路的同步時脈訊號，亦可使用在無線通訊系統上，例如本地震盪器。

Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers.

The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. Ａ synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators.

摘要…… i
Abstract ii
第一章 簡介 1
1.1研究動機與目的 1
1.2先前相關文獻討論 2
1.3論文大綱 4
第二章 使用雙門檻電壓之6-電晶體靜態記憶體及低功率止擾器 5
2.1概論 5
2.2架構簡介 9
2.2.1 SRAM記憶單元 9
2.2.2 止擾器 (Quenchers) 13
2.2.3 內建自我測試考量 14
2.2.4 SRAM架構 16
2.3模擬結果 20
2.3.1 SRAM記憶單元模擬結果 20
2.3.2 止擾器模擬結果 21
2.3.3 SRAM模擬結果 21
2.3.4 內建自我測試模擬結果 25

2.4測試結果與晶片佈局 26
2.4.1 SRAM讀寫測試 26
2.4.2 內建自我測試功能量測 31
2.4.3 晶片佈局 32
2.5結論 34
第三章 可程式化鎖相迴路式倍頻器 36
3.1概論 36
3.2架構簡介 38
3.2.1 壓控震盪器 38
3.2.2 相位頻率偵測器 40
3.2.3 電荷幫浦器與迴路濾波器 41
3.2.4 可程式化除頻器 44
3.3模擬結果與晶片佈局 48
3.3.1 模擬結果 48
3.3.2 晶片佈局 51
3.4測試結果 53
3.5結論 56
第四章 總結 57
參考文獻 58

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