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博碩士論文 etd-0626109-132754 詳細資訊
Title page for etd-0626109-132754
論文名稱
Title
直接序列極寬頻系統之基頻收發機之電路設計
Circuit Design of Baseband Transceiver for Direct Sequence Ultra-Wide Band Systems
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
94
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2008-07-31
繳交日期
Date of Submission
2009-06-26
關鍵字
Keywords
極寬頻、威特比解碼器、追蹤前置
Viterbi decoder, Trace forward
統計
Statistics
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中文摘要
本篇論文設計符合直接序列極寬頻(Direct Sequence Ultra-Wide Band, DS-UWB)系統的基頻整合晶片,其中我們針對威特比解碼器提出一個低複雜度的電路架構,此電路採用比較選擇加法單元(compare-select-add unit, CSAU)與追蹤前置架構(trace forward)。首先在比較選擇加法單元中的判斷位元決定運算,我們觀察其運算間符號的變化來做簡化,僅使用一個加法運算來降低複雜度。另外在殘存管理單元(survivor management unit, SMU)使用兩組追蹤前置,藉由排列記憶體讀取順序來變更管理方式,因此將記憶體個數簡化為兩塊長度為T的單埠記憶體,達到降低使用記憶體面積之目的。
晶片模擬是使用TSMC 0.18-μm 1P6M CMOS製程,其電路核心面積為1.061 × 1.069 mm2。在1.8伏特與25 的後佈局模擬環境下,我們提出的直接序列極寬頻系統基頻晶片其工作頻率可達到141 MHz,功率消耗為86.41 mW。
Abstract
A circuit design of baseband transceiver for direct sequence ultra-wide band system is presented in this thesis. A low complexity Viterbi decoder is also proposed. This Viterbi decoder circuit is based on compare-select-add unit and trace-forward architecture. The decision bit operator is reduced to one adder and this can lower down the hardware complexity. Further, two trace-forward operators are used in the survivor management unit. Only two single port SRAM’s with a length of T are applied for reducing the area of memory.
The chip is implemented by TSMC standard 0.18-μm 1P6M CMOS process with core area 1.061 × 1.069 mm2. The post-layout simulation with 1.8V supply at 25 shows that the proposed direct sequence ultra-wide band system of baseband transceiver chip can work above 141 MHz with 86.41 mW power dissipation.
目次 Table of Contents
誌謝 ……………………………………………………………………………….i
摘要 ………………………………………………………………………………ii
Abstract ……………………..……………………………………………………….iii
目錄 ………………………..…………………………………………………….iv
圖索引 …………………………..………………………………………………….vi
表索引 ………………………………….………………………………………….ix
第一章 緒論 1
1.1 研究背景與動機 1
1.2 各章提要 3
第二章 直接序列極寬頻系統規格與架構 4
2.1 DS-UWB實體層規格 4
2.1.1 前置序列 4
2.1.2 資料序列 6
2.1.3 混擾器 7
2.1.4 迴旋編碼器 8
2.1.5 交錯器 9
2.1.6 根餘弦濾波器 10
2.2 通道模型 13
2.3 接收機設計 17
2.3.1 訊號能量偵測 18
2.3.2 最大能量獲取 20
2.3.3 粗略通道估測 23
2.3.4 訊框起始偵測 28
2.3.5 決策回饋等化 31
第三章 威特比解碼器電路設計 43
3.1 迴旋碼編碼與解碼原理 43
3.2 威特比解碼器架構設計 44
3.2.1 分支路徑單元 45
3.2.2 比較選擇加法單元 48
3.2.3 殘存管理單元 52
第四章 系統模擬與晶片設計 61
4.1 系統整合架構 61
4.1.1 收發機資料規格與處理流程 61
4.2 接收機各階段位元決定 63
4.3 晶片設計流程 74
4.3.1 ModelSim Simulation 76
4.3.2 佈局與繞線 78
4.3.3 DRC驗證 79
4.3.4 LVS驗證 80
第五章 結論 81
參考文獻 82
參考文獻 References
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