本論文採用TSMC.18μm製程技術，分析並實作一個 13 位元， 1億次取樣速率的低功耗之類比數位轉換器電路。以逐次逼近型類比數位轉換器取代傳統的管線式類比數位轉換器中的快閃式類比數位轉換器電路作為子類比數位轉換器，提高各管線階級的位元輸出，大幅減低管線階級數量使整體電路只剩下一個高功率消耗的運算放大器。採用逐次逼近型類比數位轉換器可提高整體類比數位轉換器的精確度，並取代前端取樣保持電路更進一步降低消耗。逐次逼近型類比數位轉換器以非同步方式提高整體類比數位轉換器的轉換速度。在子類比數位轉換器取樣時期利用一個額外的動態比較器使得管線階級在相同的執行時間內多產生一個位元的輸出。
使用動態比較器技術來降低整體的功率消耗。同時使用對稱式靴帶式交換器以控制前端取樣開關，進而達到減少低電壓操作時對取樣保持電路線性度的影響。運算放大器則使用切換式運算放大器技術，藉此更進一步降低功率消耗。

In this thesis, the circuits are designing with TSMC.18μm CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100MS/s and 13-bits individually. The proposed pipelined stage replace the Flash ADC by the SAR ADC and add an extra comparator to determine most-significant-bit in the sampling phase of pipelined stage. It can greatly reduce the number of the pipelined stage and the operational amplifier which is energy-hungry in the pipelined ADC. Using the sampling signal on the top plates of capacitor array, it can eliminate the need of front-end sample and hold circuit.

The dynamic comparator is employed for the lower power consumption for whole circuit. Furthermore, the asynchronous control logic circuit is used in this pipelined ADC to free the need of an additional clock generator. The bootstrapped switch which can reduce the impacts of linearity for operating under low supply voltage. The operation amplifier implement by the partially switched-opamp technique to reduce more power consumption.

Chapter 1 Introduction 1
1.1. Motivation 1
1.2. Thesis Organization 2
Chapter 2 Review of Analog-to-Digital Converter 3
2.1. Introduction 3
2.2. General Considerations 4
2.2.1. Resolution 4
2.2.2. Quantization Error 4
2.3. Performance Metrics of Analog-to-Digital Converter 5
2.3.1. Static Performance Metrics 5
a) Offset Error and Gain Error 5
b) Integral Nonlinearity (INL) 6
c) Differential Nonlinearity (DNL) 6
d) Missing Code 7
2.3.2. Dynamic Performance Metrics 7
a) Signal-to-Noise Ratio (SNR) 7
b) Signal-to-Noise and Distortion Ratio (SNDR) 8
c) Spurious-Free Dynamic Range (SFDR) 8
d) Effective Number of Bits (ENOB) 8
2.4. Architectures of Analog-to-Digital Converter 9
2.4.1. Flash ADCs 9
2.4.2. Two-Stage ADCs 10
2.4.3. Pipeline ADCs 11
2.4.4. Successive Approximation ADCs 12
Chapter 3 The principle of designing a pipeline ADC 15
3.1. Switch 15
3.1.1. ON-Resistance 15
3.1.2. Charge Injection 16
3.1.3. Clock Feedthrough 17
3.2. Operational Amplifier 18
3.2.1. DC Gain 18
3.2.2. Bandwidth Requirement 20
3.3. Reference Voltage from Resistor 21
Chapter 4 The implementation of ADC 23
4.1 Proposed Pipelined-SAR ADC Architecture 26
4.1.1. Stage 1 Sub-ADC 26
4.1.2. First-stage 5bit MDAC implementation 29
4.1.3. Second-Stage Sub-ADC 32
4.2 Dynamic Comparator 37
4.3 Amplifiers 41
4.4 Bootstrapped Switch 46
4.5 SAR Logic controller 47
Chapter 5 Conclusion 51
References 53

[1]. G. E. Moore, “Cramming more components onto integrated circuits,” Proceedings of the IEEE, vol. 86, pp.82-85, 1998.
[2]. J. Arias, V. Boccuzzi, L. Quintanilla, L. Enriquez, D. Bisbal, M. Banu, and J. Barbolla, “Low Pipeline ADC for Wireless LANs,” IEEE Journal of .Solid-state circuits, Vol. 39, pp. 1338-1340, August 2004.
[3]. M. Mohajerin, C. Chen and E. Abdel-Raheem, “A new 12-b 40 MS/s, low-power, low-area pipeline ADC for video analog front ends,” IEEE Pacific Rim Conference, pp.597 – 600, Aug. 2005.
[4]. B.K Ahuja, et al., “A 30 Msample/s 12b 110 mW video analog front end for digital camera,” IEEE International Conference of Solid-State Circuits, Vol.1, pp.438 – 479, Feb. 2002.
[5]. D. Kurose, et al., “55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers,” IEEE Journal of Solid-State Circuits, Vol.41, No.7, pp.1589 – 1595, July. 2006.
[6]. J. Francke, Y. Huazhong and L. Rong, “A 10-Bit, 40 MSamples/s Low Power Pipeline ADC for System-on-a-Chip Digital TV Application,” International Semiconductor Conference, Vol.2, pp.421 – 424, Sept. 2006.
[7]. M. Trojer, M. Cleris, U. Gaier, T. Hebein, P. Pridnig, B. Kuttin, B. Tschuden, C. Krassnitzer, C. Kuttin, W. Pribyl, “A 1.2V 56mW 10 bit 165Ms/s pipeline-ADC for HD-video applications,” Solid-State Circuits Conference,2008. ESSCIRC 2008. 34th European, pp.270 – 273, Sept. 2008.
[8]. B. Razavi, “Principles of Data Conversion System Design,” NJ: IEEE Press, 1995.
[9]. P. Lowenborg, Mixed-Signal Processing Systems, Linkoping University, 2006
[10]. Kent. H. Lundsberg, Analog-to-Digital Converters Testing, 2002.
[11]. “IEEE standard for terminology and test methods for analog-to-digital converters”, IEEE Instrumentation and Measurement Society of Waveform Measurement and Analysis Technical Committee, June. 2001.
[12]. R.J. BAKER, “CMOS Circuit Design, Layout, and Simulation Third Edition”, John Wiley, 2010.
[13]. D. A. Johns, K. Martin, “Analog Integrated Circuit Design”, John Wiley & Sons, 1997.
[14]. S. Rapuano, et al, “ADC parameter and Characteristics,” IEEE instrumentation & Measurement Magazine, Vol.8, No.5, pp.44 – 54, Dec. 2005.
[15]. Maxim, “Defining and Testing Dynamic Parameters in High-Speed ADCs, part 1”, tutorial 728, 2001.
[16]. P.E. ALLEN, “CMOS Analog Circuit Design, 2nd,” Oxford University Press, 2002.
[17]. S.H. Lewis and P.R. Gray, “A Pipelined 5-Msample/s 9-bit analog-to-digital converter,” IEEE Journal of Solid-State Circuits, Vol.22, No.6, pp.954 – 961, Dec. 1987.
[18]. A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE Journal of Solid-State Circuits, Vol. 34, No.5, pp. 599-606, May 1999.
[19]. T.B. Cho and P.R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” IEEE Journal of Solid-State Circuits, Vol.30, No. 3, pp.166 – 172, March. 1995.
[20]. M. Furuta, M. Nozawa, T. Itakura, “A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique”, IEEE Journal of Solid-State Circuits, Vol. 46, No. 6, June 2011.
[21]. C. C. Lee, M. P. Flynn, “A SAR-Assisted Two-Stage Pipeline ADC”, IEEE Journal of Solid-State Circuits, Vol. 46, No. 4, April 2011.
[22]. Y. D. Jeon, “A 9.15mW 0.22mm2 10b 204MS/s Pipelined SAR ADC in 65nm CMOS,” in IEEE CICC, Sept. 2010, pp. 1-4.
[23]. S. H. Cho, C. K. Lee, “A 550-μW 10-b 40MS/s SAR ADC With Multistep Addition-Only Digital Error Correction”, IEEE Journal of Solid-State Circuits, Vol. 46, No. 8, pp. 1881-1892, Aug. 2011.
[24]. G.Z.Huang, P.F.Lin, “A Fast Bootstrapped Switch for High-Speed High Resolution A/D Converter,” IEEE Asia Pacific Conference on Circuits and Systems, pp.382-385, 2010
[25]. B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill Co.Inc, pp.420 – 421, pp.37 – 39, 2001.
[26]. O.A. Adeniran and A. Demosthenous, “Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs,” European Conference of Circuit Theory and Design, pp.55 – 58, Vol.2, Sept. 2005.
[27]. Y. Chouia, et al., “14 b, 50 MS/s CMOS front-end sample and hold module dedicated to a pipelined ADC,” Midwest Symposium of Circuits and Systems, Vol.1, pp.353 – 361, July. 2004.
[28]. C.J.B. Fayomi, G.W. Roberts, and M. Sawan, “Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization,” IEEE International Symposium of Circuits and Systems, Vol. 3, pp.2200 – 2203, May. 2005.
[29]. T.N. Andersen, et al., “A cost-efficient high-speed 12-bit pipeline ADC in 0.18 μm Digital CMOS,” IEEE Journal of Solid-State Circuits, Vol.40, No.7, pp.1506 – 1513, July. 2005.
[30]. L. Sumanen, M. Waltari and K. Halonen, “A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters,” IEEE International Conference of Electronics, Circuits and Systems, Vo.1, pp.32 – 35, Dec. 2000.
[31]. L. Sumanen, et al., “CMOS dynamic comparators for pipeline A/D converters,” IEEE International Symposium of Circuits and Systems, Vol.5, pp.157 - 160, May. 2002.
[32]. R. Lotfi, et al., “A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters,” International Symposium of Signals, Circuits and Systems, Vol. 2, pp.377 – 380, July. 2003.
[33]. C. Wulff and C. Ytterdal, “0.8V 1GHz dynamic comparator in digital 90nm CMOS technology,” NORCHIP Conference, 23rd, pp.237 – 240, Nov. 2005.
[34]. T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,” IEEE Journal of Solid Circuits, Vol. 28, No. 4, pp. 523-527, Apr. 1993.
[35]. C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure”, IEEE Journal of Solid-State Circuits, Vol. 45, No. 4, April 2010.
[36]. S. Mallya and J.H. Nevin, “Design procedures for a fully differential folded-cascode CMOS operational amplifier,” IEEE Journal of Solid-State Circuits, Vol.24, No. 6, pp.1737 – 1740. Dec. 1989.
[37]. R.V.D. Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd,” Kluwer Academic Publ, pp.521 – 522, March. 2003.
[38]. M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei, “A pseudo-class-AB telescopic-cascode operational amplifier,” International Symposium of Circuits and Systems, Vol.1, pp.737 – 740, May. 2004
[39]. J. Wang and Y. Qiu, “Analysis and design of fully differential gain-boosted telescopic cascode opamp,” International Conference of Solid-State and Integrated Circuits Technology, Vol.2, pp.1457 – 1460, Oct. 2004.
[40]. S. Runhua and L. Peng, “A gain-enhanced two-stage fully-differential CMOS op amp with high unity-gain bandwidth,” IEEE International Symposium of Circuits and Systems, V ol.2, pp.428 – 431, May. 2002.
[41]. B. Shem-Tov, M. Kozak, and E.G. Friedman, “A high-speed CMOS op-amp design technique using negative Miller capacitance,” IEEE International Conference of Electronics, Circuits and Systems, pp.623 – 626, Dec. 2004.
[42]. H. V. de Vel, B. A. J. Buter, H. vad der Ploeg, M. Vertregt, G. J. G. M. Geelen, E. J. F. Paulus, “A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 4, pp. 1047-1056, Apr. 2009.
[43]. D. Gubbins, B. Lee, P. K. Hanumolu, U.-K. Moon, “Continuous-Time Input Pepeline ADCs,” IEEE Journal of Solid-State Circuits, Vol. 45, No. 8, pp. 1456-1468, Aug. 2010.
[44]. T. Morie, T. Miki, K. Matsukawa, Y. Bando, T. Okumoto, K. Obata, S. Sakiyama, S. Dosho, “A 71db-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR Enhancement Techniques Utilizing Noise,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 272-273, Feb. 2013.
[45]. J. Oliveira, J. Goes, M. Figueiredo, E. Santin, J. Fernandes, J. Ferreira, “An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification,” IEEE Transactions on Circuits and Systems II, Vol. 57, No. 2, pp. 105-109, Feb. 2010.
[46]. Y. Miyahara, M. Sano and K. Koyama, “Adaptive Cancellation of Gain and Nonlinearity Errors in Pipelined ADCs,” IEEE International Solid-State Circuits Conference, pp.282-283, Feb. 2013.