本論文的第一部份，提出一個具有負載最佳化VCO之低jitter 5V 500 MHz 實用數位鎖相迴路。該電路可達到低jitter與快速鎖定的效果。

第二部分提出一個Half-swing PLA電路。在兩個NOR平面間我們加入一個1/2*VDD電壓源與一個做為緩衝器用的傳輸閘來消除追繞問題並且使得輸出端的上升時間與下降時間一樣。這些效果使得整體速度提升並且可以降低動態消耗功率。

第三部分以第二部分所提出的架構為基礎建構一個1.0 GHz 管線化8-bit CLA加法器。在1.0 GHz的時脈下該電路可以在兩個週期內（2.0 ns）完成兩個八位元加法運算。

The first topic of this thesis is a practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop. Besides the low jitter advantage, the design also possesses another feature, i.e., fast locked time.

The second topic is the half-swing PLA circuit. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes of PLAs to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced.

The third topic is a novel design of a the 1.0 GHz pipelining 8-bit CLA based on the architecture we mentioned in the second topic. The operating clock frequency is 1.0 GHz and the output of the addition of two 8-bit binary numbers is done in 2 cycles ( 2.0 ns ).

中文摘要…………………………………………. i
英文摘要………………………………………… ii
第一章 簡介 1
1.1 前言 1
1.2 論文目的 1
1.3 論文大綱 2
第二章 具有負載最佳化VCO之低jitter 5V 500 MHz實用數位鎖相迴路 3
2.1 概論 3
2.2 設計構想與晶片架構設計 4
2.2.1. 在OSC中加入頻率限制器 4
2.2.2. 具負載最佳化之3-stage 反相器之VCO 5
2.2.3. 快速鎖定考量與補償 6
2.3 模擬結果 7
2.4 測試結果 8
2.5 結論 8
第三章 低功率高速的編解碼電路 17
3.1 概論 17
3.2 PLA架構 18
3.2.1現況 18
3.2.2 Half-swing PLA架構 19
3.3速度與功率消耗分析 22
3.3.1速度分析 22
3.3.2功率消耗分析 22
3.4模擬與分析 24
3.5結論 27
第四章 以Half-swing PLA架構設計之1.0 GHz Pipelining 8-bit CLA加法器 36
4.1 概論 36
4.2以Half-swing PLA架構之8-bit CLA加法器 37
4.2.1電路設計考量 38
4.3 模擬結果與晶片佈局 40
4.4 結論 42
第五章 結論 49
參考文獻 51

[1] Z.-X. Zhang, H. Du, and M. S. Lee, “A 360MHz 3V CMOS PLL with 1V peak-to-peak power supply noise tolerance,” 1996 Inter. Symp. on Solid-State Circuits, pp. 134-135, 1996.
[2] V. von Kaenel, D. Aebischer, R. van Dongen, and C. Piguet, “A 600MHz CMOS PLL microprocessor clock generator with a 1.2GHz VCO,” 1998 Inter. Symp. on Solid-State Circuits, pp. 320-323, 1998.
[3] J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, “A wide-bandwidth low-voltage PLL for PowerPC microprocessors,” IEEE J. of Solid-State Circuits, vol. SC-30, pp. 383-391, Apr. 1995.
[4] V. von Kaenel, D. Aebischer, C. Piguet, and E. Dijkstra, “A 320 MHz, 1.5 mW @ 1.35V CMOS PLL for microprocessor clock generation,” IEEE J. of Solid-State Circuits, vol. 31, no. 11, pp.1715-1722, Nov. 1996.
[5] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. of Solid-State Circuits, vol. 31, no. 11, pp.1723-1732, Nov. 1996.
[6] H. O. Johansson, “A simple precharged CMOS phase frequency detector,” IEEE J. of Solid-State Circuits, vol. 33, no. 2, pp.295-299, Feb. 1998.
[7] A. Waizman, “A delay line loop for frequency synthesis of de-skewed clock,” 1994 Inter. Symp. on Solid-State Circuits, pp. 298-299, 1994.
[8] H. C. Yang, L. K. Lee, and R. S. Co, “A low jitter 0.3-165MHz CMOS PLL frequency synthesizer for 3V/5V operation,” IEEE J. of Solid-State Circuits, vol. 32, no. 4, pp.582-586, Apr. 1997.
[9] R. J. Baker, H. W. Li, and D. E. Boyce, “CMOS circuit design, layout, and simulation,” Reading : IEEE Press, 1998.
[10] M. Afghahi, “A robust single phase clocking for low power, high-speed VLSI applications,” IEEE J. of Solid-State Circuits, vol. 31, no. 2, pp.247-253, Feb. 1996.
[11] G. M. Blair, “PLA design for single-clock CMOS,” IEEE J. of Solid-State Circuits, vol. 27, no. 8, pp.1211-1213, Aug. 1992.
[12] Y. B. Dhong, and C. P. Tsang, “High speed CMOS POS PLA using predischarged OR array and charge sharing AND array,” IEEE Trans. on Circuits & Systems –II: Analog and Digital Signal Processing, vol. 39, no. 8, pp. 557-564, Aug. 1992
[13] C.-C. Wang, C.-F. Wu, R.-T. Hwang, and C.-H. Kao, “A low-power and high-speed dynamic PLA circuit configuration for single-clock CMOS,” 1997 National Computer Symposium (NCS’97), vol. 2, pp. C-57-C-62, Dec. 1997.
[14] K. Bernsteinr, K. M. Carrig, et al., “High speed CMOS design styles,” Reading. Kluwer Academic Publishers, 1998, pp. 36-47.
[15] U. Ko, P. T. Balsara, and W. Lee, “Low-power design techniques for high-performance CMOS adders,” IEEE Tran. on Very Large Scale Integration (VLSI) Systems, vol. 32, pp. 327-333, June. 1995.
[16] W. Hwang, D. Gristede, P. Sanda, S. Y. Wang and D. F. Heidel, “Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability,” IEEE J. of Solid-State Circuits,Vol. 34, No. 8, pp. 1108-1117, Aug. 1999.
[17] Z. Wang, G. A. Jullien, W. C. Miller, J. Wang and S. S. Bizzan, “Fast adders using enhanced multiple-output domino logic, ” IEEE J. of Solid-State Circuits, vol. 32, No. 2, pp. 206~214, Feb. 1997.
[18] C.-C. Wang, and K.-C. Tsai, “VLSI design of a 1.0 GHz 0.6um 8-bit CLA using PLA-styled all-N-transistor logic,” 1998 IEEE Inter. Symp. on Circuits & Systems (ISCAS'98), vol. 2, pp. 236-239, Jun. 1998.
[19] C.-C. Wang, Y.-T. Chien, and Y.-P. Chen, “A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop, 1999 IEEE Inter. Symp. on Circuits & systems, vol. II, pp.528-531, June. 1999.
[20] C.-C. Wang, Y.-T. Chien, and Y.-P. Chen, “Power-saving fast half-swing inter-plane circuit for clocked PLAs,” 1999 Symp. of Microprocessor Design, pp.141-148, May 1999.
[21] C.-C. Wang, Y.-T. Chien, and Y.-P. Chen, Design of an inter-plane circuit for clocked PLAs," 2000 IEEE Inter. Symp. on Circuits and Systems (ISCAS'2000), (accepted, no. 158).