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博碩士論文 etd-0627102-185433 詳細資訊
Title page for etd-0627102-185433
論文名稱
Title
數值模擬覆晶晶粒尺寸封裝之熱疲勞問題
Numerical Simulation on Thermal Fatigue of a Flip Chip Scale Packaging
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
66
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2002-06-21
繳交日期
Date of Submission
2002-06-27
關鍵字
Keywords
覆晶封裝、熱疲勞
Fatigue, Flip Chip
統計
Statistics
本論文已被瀏覽 5693 次,被下載 5033
The thesis/dissertation has been browsed 5693 times, has been downloaded 5033 times.
中文摘要
摘 要
本文係針對覆晶晶粒尺寸封裝在溫度循環作用下,利用有限元素分析軟體ANSYS進行數值模擬,先探討二維與三維結構之差異性,再以覆晶晶粒尺寸封裝體內錫鉛凸塊之位置、高度及溫度循環頻率為參數,對覆晶晶粒尺寸封裝體之各種疲勞模型及疲勞損傷的影響進行評估。
研究結果顯示,就二維與三維結構之差異性而言,簡化的二維模型可幫助了解結構最大位移及最大等效應變的位置,但其值仍有一定的誤差。對整體而言,最先產生疲勞破壞的位置為距離對稱中心最遠處之錫鉛凸塊上方。就錫鉛凸塊的高度而言,高度越低越容易產生疲勞破壞。就溫度循環頻率而言,在高低溫時所停留的時間越長越容易產生潛變疲勞破壞。經本文三維數值模擬各種疲勞模型之結果,發現對於錫鉛凸塊高度的改變會使得錫鉛凸塊塑性應變所造成的疲勞損傷比潛變所造成的疲勞損傷產生更明顯的變化。而當溫度循環在高低溫時所停留的時間延長則會增加錫鉛凸塊潛變所造成的疲勞損傷,但不影響錫鉛凸塊塑性應變所造成的疲勞損傷。至於溫度循環所造成的疲勞損傷則會因錫鉛凸塊高度的降低或溫度循環在高低溫時所停留的時間延長而增加。






Abstract
Abstract
The thesis is aimed to simulate the flip chip in chip scale package (FCCSP) by finite element method incorporated with software ANSYS due to thermally cyclic loading. The difference between two-dimensional and tree-dimensional structures is conferred. The position and height of solder bump in FCCSP and cyclic temperature are considered as parameters. The effects of above-mentioned parameters on package’s fatigue models and fatigue damage are studied.
The results show that the two-dimensional structure can help us to understand the position of the maximum displacement and the maximum equivalent strain. However, the values of numerical result in the two- dimensional structure are not very accurate. The fatigue fracture will first take place at the top of the most outside solder bump far away from the center of the whole package. If the height of solder bump is lower, the fatigue fracture of solder bump is faster. If the duration time of high and low temperatures is longer, the fatigue fracture due to creep of solder bump becomes faster. When the height of solder bump is change, the change of fatigue damage with plastic strain of solder bump will more obvious than the change of fatigue damage due to creep of solder bump. The extension of duration time of high and low temperatures will increase fatigue damage due to creep of solder bump, but not change the fatigue damage with plastic strain of solder bump. When the height of solder bump is reduced or the duration time of high and low temperatures is extended will increase fatigue damage subjected to cyclic temperature.



目次 Table of Contents
目錄
目錄 ………………………………………………………………Ⅰ
表目錄 ………………………………………………………………Ⅳ
圖目錄 ………………………………………………………………Ⅴ
摘要 ………………………………………………………………Ⅷ
英文摘要 …………………………………………………………Ⅸ
第一章 緒論 …………………………………………………… 1
1-1 前言 ………………………………………………… 1
1-2 封裝簡介 …………………………………………… 2
1-2-1 IC封裝 …………………………………………… 2
1-2-2 覆晶晶粒尺寸封裝之介紹及製程 …………… 2
1-3 封裝之可靠度實驗 ………………………………… 3
1-4 研究方向 ……………………………………………… 4
1-5 文獻回顧 ………………………………………………5
1-6 組織與章節 ……………………………………………6
第二章 理論部分 ………………………………………………10
2-1 線性與非線性分析理論 ……………………………10
2-1-1應力應變曲線 ………………………………10
2-1-2降伏點規範 …………………………………11
2-1-3線性分析理論 ………………………………11
2-1-4非線性分析理論 ………………………………12
2-2 疲勞破壞理論 …………………………………………15
2-2-1 三維應力應變關係 ……………………………16
2-2-2 疲勞模型…………………………………………17
2-2-3 應變疲勞模型 …………………………………18
2-3 累積損傷理論 ……………………………………19
第三章 數值模擬 … …………………………………………25
3-1 基本假設 ……………………………………………26
3-2 模型架構 ……………………………………………26
3-3 ANSYS有限元素分析軟體 …………………………28
3-3-1 有限元素分析 …………………………………28
3-3-2 ANSYS分析步驟 ………………………………29
第四章 結果與討論 …………………………………………40
4-1 模擬結果的收斂性分析 ……………………………40
4-2 2D結構與3D結構之差異性分析 …………………41
4-3 錫鉛凸塊之結構分析 ………………………………42
4-4 疲勞模式之分析 ……………………………………43
第五章 結論與未來展望 ……………………………………62
5-1 結論 ………………………………………………62
5-2 未來展望 …………………………………………63

參考文獻 ……………………………………………………………64

參考文獻 References
參考文獻
1. 蘇必俠,”國內凸塊封裝技術報導”, 電子月刊第五卷第十一期.
2. 郭嘉龍,”半導體封裝工程”, 全華科技圖書, 台北, pp.1-3, 1999.
3. 郭嘉龍,”圖解SMT接合材料入門”, 全華科技圖書, 台北, 2000.
4. 葉繞謙,”覆晶晶粒尺寸構裝之熱應力分析”, 國立中山大學機械工程研究所碩士論文, 2001.
5. 劉業繡、林光隆,”銲錫可靠度分析”, 電子月刊第五卷第十一期.
6. W. T. Chen and C. W. Nelson,“Thermal Stress In Bonded Joints”, IBM Journal of Research and Development, Vol.23, No.2, pp.179-188, 1979.
7. A. Kuo,“Thermal Stress at the Edge of a Bimetallic Thermostat”, Journal of Applied Mechanics, Vol.56, pp.585-589, 1989.
8. Darbha Suryanaryana, Richard Hsiao, Thomas P. Gall and Jack M. McCreary, “Enhancement of Flip-Chip Fatigue Life by Encapsulation”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 14, No.1, pp.218-223,1991.
9. J. H. Lau and D. W. Rice,“Thermal Fatigue Life Prediction of Flip Chip Solder Joints by Fracture Mechanics Method”, Advances in Electronic Packaging ASME, pp.385-392, 1992.
10. J. H. Lau,“Flip Chip Technologies”, McGraw-Hill Companies, Inc. New York, 1997.
11. M. Ikemizu, Y. Fukuzawa and J. Nakano,“CSP Solder Ball Reliablity”, Thshiba Corporation, IEEE, pp.447-451, 1997.
12. J. H. Lau and Yi-Hsin Pao,“Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies”, McGraw-Hill Companies, Inc. New York, 1997.
13. John H.L. Pang and Tze-Ing Tan, ”Thermal-Mechanical Analysis of Solder Joint Fatigue and Creep in a Flip Chip On Board Package Subjected to Temperature“, IEEE Electronic Components and Technology Conference, pp.878-883, 1998.
14. S. Rzepka, M. A. Korhonen, E. Meusel and C. -Y. Li,“The Effect Underfill and Underfill Delamination on the Thermal Stress in Flip-chip Solder Joints”, Transactions on ASME Journal of Electronic Packaging, Vol.120, pp.342-348, 1998.
15. Zhengfang Qian, Minfu Lu, Wei Ren and Sheng Liu,“Fatigue Life Prediction of Flip-Chip in Terms of Nonlinear Behaviors of solder and Underfill”, IEEE Electronic Components and Technology conference, pp.141-148, 1999.
16. E.T. Ong, A.A.O. Tay,“Effect of Delamination on the Thermal Fatigue of Solder Joints in Flip Chips”, IEEE 2000 Inter Society Conference on Thermal Phenomer, pp200-207, 2000.
17. Kuo-Ning Chiang and Chang-Ming Liu,“Solder Shape Design and Thermal Stress/Strain Analysis of Flip Chip Packaging Using Hybrid Method”, 2000 Int’l Symposium on Electronic Materials & Packaging, pp.44-50, 2000.
18. ANSYS Menu,“Newton-Raphson Procedure”, ANSYS Theory Reference, Reversion 5.5, pp.15-28-40, 1998.
19. 朱紹鎔譯,”材料力學”, 東華書局, 71年4月.
20. J. H. Lau and Shi-Wei R. Lee,“Chip Scale Package, CSP: design, materials, processes, reliability and applications”, McGraw-Hill Companies, Inc. New York, 1999.
21. L. F. Coffin, Jr., ”A Study of Effects of Cyclic Thermal Stress on a Ductile Metal”, Trans. ASME, Vo176. pp.931-950,1954.
22. O. H. Basquin, ”The Exponential Law of Endurance Tests”, Am. Soc. Test. Master. Proc., Vol.10, pp.625-630,1910.
23. W. Engelmaier, ”Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol.CHMT-6, No.3, pp.52-57,1983.
24. Solomon, H. D.,”Fatigue of Solder“ , IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol.9, No.4, pp.423-432,1986.
25. John H. L. Pang, ”CBGA Solder Joint Reliability Evaluation Based on Elastic-plastic-Creep Analysis”, Trans. ASME,Vol.122, pp.255-261, 2000.
26. 范欽珊主編,”工程力學Ⅱ”, 五南圖書, 台北, pp.403-421, 1999.
27. H. U. Akay, N. H. Paydar, A.Bilgic, ”Fatigue Life Predictionfor Thermally Loaded Solder Joints Using a Volume-Weighted Averaging Technique”, Trans. ASME,Vol.119, pp.228-235, 1997.
28. Z.N.Chen and G.Z.Wang, ”Influences of Packaging Materials on the Solder Joint Reliability of Chip Scale Package Assemblies”, International Symposium on Advanced Packaging Materials, 1999.
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