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博碩士論文 etd-0627108-201016 詳細資訊
Title page for etd-0627108-201016
論文名稱
Title
具優質本體縛點、埋入式阻絕層和新穎嵌入式閘極的垂直式側邊環繞閘極金氧半場效電晶體之性能研討
The Characterization of the Vertical Sidewall MOSFETs with Smart Body-tie, Buried Block Layer, and Novel Embedded Gate
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
89
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2008-06-13
繳交日期
Date of Submission
2008-06-27
關鍵字
Keywords
金氧半場效電晶體、自我加熱效應、本體縛點、垂直島狀物
floating body, kink
統計
Statistics
本論文已被瀏覽 5651 次,被下載 8
The thesis/dissertation has been browsed 5651 times, has been downloaded 8 times.
中文摘要
在本論文中我們根據垂直式金氧半場效電晶體的發展,提出幾種具有垂直式通道、雙閘極、和採用埋入式絕緣層或矽覆絕緣層的金氧半場效電晶體來解決傳統場效電晶體在開關元件、CMOS技術、記憶體和功率元件等應用下的缺點。由於垂直式側邊環繞閘極金氧半場效電晶體具有減少製程面積的優點並提供多通道的統整製程;以離子佈植控制通道長度來避免傳統元件於極小通道長度下光罩微縮的成本耗損。故本論文基於此條件下提出:1.具優質源/基極縛點的矽覆絕緣垂直式金氧半場效電晶體(SSBVMOS):提供不多占面積的本體縛點,來將多餘載子逸除,並供給散熱的有效途徑,以解決垂直式仍然受傳統浮體效應和自我加熱效應的缺點。我們調整垂直通道長度、改變矽覆氧化層厚度、並與傳統垂直架構作比較,整理研究此架構的優良電性和模擬數據。2.具有內襯氧化層的垂直式側邊環繞閘極金氧半場效電晶體(ULVMOS):使用內襯氧化絕緣層來克服多餘PN接面所造成的接面漏電流,並提供類似於全空乏通道的垂直電流導通區域以提供優越的元件特性。3.具嵌入式閘極的垂直式側邊環繞閘極金氧半場效電晶體(EGVMOS):在維持傳統垂直結構的優點下,再減少垂直結構的製程困難度,並期能克服以往側邊環繞垂直元件的重疊電容問題。
同時我們利用ISE-TCAD模擬軟體模擬提出元件的所有數據以及其詳細製程,並透過量測軟體製作電性曲線圖以及圖表以及部分實做,證實提出的新架構能夠克服以往場效電晶體的電性缺失,而獲得優良的次臨界擺幅、開關電流比例、DIBL…等元件優越特性。希望在愈益微縮的半導體元件發展下,能提供有效的應用。
Abstract
In this thesis, according to the development of the vertical MOSFETs, we propose several MOSFETs that possess vertical channels, double gates, and buried oxide to solve the defects of the applications in switch devices, CMOS technique, and power devices.
The vertical sidewall MOSFETs has many advantages, such as the packing density improvement, multiple channels, and independence on the critical lithography. Based on these characteristics, three kinds MOSFETs are now proposed. The first one is the vertical SOI MOSFET with smart source/ body contact (SSBVMOS). It is proposed to solve the floating body effect and self-heating effect. SSBVMOS provides a body-tie that does not occupy the excessive wafer area. It uses the smart source/body-tie to eliminate the unnecessary carriers and to provide an effective heat pass way. In addition, SSBVMOS is discussed with respect to the channel length and the buried oxide thickness adjustments, and also compared with the conventional vertical sidewall MOSFETs. The second one is the vertical MOSFET with upper and internal l-shape buried oxide (ULVMOS). ULVMOS uses the buried oxide to decrease the junction leakage. The ULVMOS also operates under the fully depleted regime to provide good characteristics. The last one is the novel embedded vertical sidewall MOSFETs (EGVMOS). EGVMOS maintains the advantages of the vertical structures and reduces the fabrication difficulty. It is also expected to decrease the overlap capacitance issue which affects the AC performance in the vertical sidewall MOSFET.
As semiconductor channel length scaled down, the proposed devices is proved to provide effective applications for achieving good subthreshold swing, high on-off current ratio, and low DIBL through ISE-TCAD software simulation and real fabrication.
目次 Table of Contents
第一章 緒論 ___01
1.1 論文評論 ___02
1.1.1垂直式金氧半場效電晶體 ___02
1.1.2矽覆絕緣金氧半場效電晶體 ___05
第二章 元件設計和製程 ___10
2.1 源由 ___10
2.1.1具有優質源/基極缚點的矽覆絕緣垂直式金氧半場效電晶體(SSBVMOS) ___10
2.1.2具有內襯氧化層的垂直式側邊環繞閘極金氧半場效電晶體(ULVMOS) ___12
2.1.3具嵌入式閘極的垂直式側邊環繞閘極金氧半場效電晶體
(EGVMOS) ___13
2.2 元件FLOOPS TCAD 2-D模擬設計 ___15
2.2.1 SSBVMOS ___15
2.2.2 ULVMOS ___18
2.2.3 EGVMOS ___19
2.3 SSBVMOS元件實作 ___20
2.3.1 元件實作考量 ___20
2.3.2實作N型金氧半場效電晶體的製程 ___21
2.4 結論 ___22

第三章 結果與探討 ___23
3.1 元件DESSIS TCAD模擬結果 ___23
3.1.1 SSBVMOS ___23
3.1.2 ULVMOS ___37
3.1.3 EGVMOS ___43
3.2 SSBVMOS實作結果 ___48
3.3 元件結果討論 ___55
3.3.1 SSBVMOS ___55
3.3.2 ULVMOS ___55
3.3.3 EGVMOS ___56
3.4 結論 ___56
第四章 總結 ___57
第五章 垂直式金氧半場效電晶體的未來發展 ___58
參考文獻 ___60
附錄 ___64
A:具有優質源/基極缚點的矽覆絕緣垂直式金氧半場效電晶體(SSBVMOS)製程單 (run card) ___64
B:個人著作 ___79
B.1 論文發表目錄 ___79
B.2發表論文全文 ___80
參考文獻 References
[1] http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_PIDS.pdf
[2] The International Technology Roadmap for Semiconductors: 2007
[3] Borkar, S.; “Obeying Moore's law beyond 0.18 micron [microprocessor design]”, ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 13-16 Sept. 2000, Page(s):26 - 31
[4] Ostling, M.; Malm, B.G.; von Haartman, M.; Hallstedt, J.; Zhen Zhang; Hellstrom, P.-E.; Shili Zhang; “Device Integration Issues Towards 10 nm MOSFETs” , Microelectronics, 2006 25th International Conference , 14-17 May 2006, Page(s):23 - 28.
[5] Leobandung, E.; Chou, S.Y.; “Reduction of short channel effects in SOI MOSFETs with 35 nm channel width and 70 nm channel length”, Device Research Conference, 1996. Digest. 54th Annual, 24-26 June 1996, Page(s):110 - 111
[6] Mori, K.; “Vertical MOS transistor with threshold voltage adjustment”, Electronics Manufacturing Technology Symposium, 1999. Twenty-Fourth IEEE/CPMT, 18-19 Oct. 1999, Page(s):245 – 248.
[7] Hergenrother, J.M.; Monroe, D.; Klemens, F.P.; Komblit, A.; Weber, G.R.; Mansfield, W.M.; Baker, M.R.; Baumann, F.H.; Bolan, K.J.; Bower, J.E.; Ciampa, N.A.; Cirelli, R.A.; Colonell, J.I.; Eaglesham, D.J.; Frackoviak, J.; Gossmann, H.J.; Green, M.L.; Hillenius, S.J.; King, C.A.; Kleiman, R.N.; Lai, W.Y.C.; Lee, J.T.-C.; Liu, R.C.; Maynard, H.L.; Morris, M.D.; Oh, S.-H.; Pai, C.-S.; Rafferty, C.S.; Rosamilia, J.M.; Sorsch, T.W.; Vuong, H.-H.; “The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length”, Electron Devices Meeting, 1999. IEDM Technical Digest. International, 5-8 Dec. 1999, Page(s):75 – 78.
[8] Lizhe Tan; Buiu, O.; Hall, S.; Gili, E.; Ashburn, P.; “A technology for building shallow junction MOSFETs on vertical pillar walls”, Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on, Oct. 2006, Page(s):472 – 474.
[9] Schulz, T.; Rosner, W.; Risch, L.; Langmann, U.; “50-nm vertical sidewall transistors with high channel doping concentrations”, Electron Devices Meeting, 2000. IEDM Technical Digest. International, 10-13 Dec. 2000, Page(s):61 – 64.
[10] Scheinert, S.; Paasch, G.; Kittler, M.; Nuernbergk, D.; Mau, H.; Schwierz, F.; “Requirements and restrictions in optimizing homogeneous and planar doped barrier vertical MOSFETs”, Devices, Circuits and Systems, 1998. Proceedings of the 1998 Second IEEE International Caracas Conference, 2-4 March 1998, Page(s):55 – 58.
[11] Duan, F.L.; Zhao, X.; Ioannou, D.E.; “Increased channel edge impact ionization in SOI MOSFET's and effects on device operation”, SOI Conference, 1998. Proceedings., 1998 IEEE International, 5-8 Oct. 1998, Page(s):171 – 172.
[12] Nakajima, H.; Yanagi, S.; Komiya, K.; Omura, Y.; “Off-leakage and drive current characteristics of sub-100-nm SOI MOSFETs and impact of quantum tunnel current”, Electron Devices, IEEE Transactions, Volume 49, Issue 10, Oct. 2002, Page(s):1775 – 1782.
[13] Xiaowu Cai; Chaohe Hai; “Study of body contact of partial depleted SOI NMOS devices”, Solid-State and Integrated Circuit Technology, Oct. 2006 Page(s):212 - 214
[14] Dunga, M.V.; Kumar, A.; Ramgopal Rao, V.; “Analysis of floating body effects in thin film SOI MOSFETs using the GIDL current technique”, Physical and Failure Analysis of Integrated Circuits, 2001. IPFA 2001. Proceedings of the 2001 8th International Symposium, 9-13 July 2001, Page(s):254 – 257.
[15] Xu, X.; Widenhofer, R.; Rashed, M.; Jallepalli, S.; Thorn, J.; Mendicino, M.; Candelaria, J.; “Impact of channel doping and Ar implant on device characteristics of partially depleted SOI MOSFETs”, SOI Conference, 1998. Proceedings., 1998 IEEE International, 5-8 Oct. 1998, Page(s):115 – 116.
[16] R. R. Troutman, Latch-up CMOS Technology, Kluwer, Boston, 1986.
[17] Elewa, T.; Balestra, F.; Cristoloveanu, S.; Hafez, I.M.; Colinge, J.-P.; Auberton-Herve, A.-J.; Davis, J.R.; “Performance and physical mechanisms in SIMOX MOS transistors operated at very low temperature”, Electron Devices, IEEE Transactions, Volume 37, Issue 4, April 1990, Page(s):1007 – 1019.
[18] Son, Y.D.; Kyung Dong Yang; Byung Seong Bae; Jang, J.; Munpyo Hong; Sung Jin Kim; “Depletion-mode TFT made of low-temperature poly-Si”, Electron Devices, IEEE Transactions, Volume 53, Issue 5, May 2006, Page(s):1260 – 1262.
[19] Young, K.K.; “Analysis of conduction in fully depleted SOI MOSFETs”, Electron Devices, IEEE Transactions, Volume 36, Issue 3, March 1989, Page(s):504 – 506.
[20] Hakim, M.M.A.; de Groot, C.H.; Gili, E.; Uchino, T.; Hall, S.; Ashburn, P.; “Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation”, Electron Devices, IEEE Transactions, Volume 53, Issue 4, April 2006 Page(s):929 - 932
[21] Xiaoyu Hou; Falong Zhou; Ru Huang; Xing Zhang; “Corner effects in vertical MOSFETs”, Solid-State and Integrated Circuits Technology, Volume 1, 18-21 Oct. 2004 Page(s):134 - 137 vol.1
[22] Su, P.; Goto, K.; Sugii, T.; Hu, C.; “Self-heating enhanced impact ionization in SOI MOSFETs”, SOI Conference, 2001 IEEE International, 1-4 Oct. 2001, Page(s):31 – 32.
[23] Jyi-Tsong Lin, and Kuo-Dong Huang, “The Effect of a Smart Body Tie on the Bottom Gate Thin Film Transistor”, Solid-State Electronics, Vol. 52 (2008) December 2007, PP. 808–812.
[24] Jyi-Tsong Lin, Kao-Cheng Lin, Tai-Yi Lee, and Yi-Chuen Eng, “Investigation of the Novel Attributes of a Vertical MOSFET with Internal Block Layer (bVMOS): 2-D Simulation Study,” in Proc. Int. Conf. Microelectronics (MIEL 2006), vol. 2, May 2006, Page(s): 488–491.
[25] Jae Young Song; Woo Young Choi; Ju Hee Park; Jong Duk Lee; Byung-Gook Park; “Design optimization of gate-all-around (GAA) MOSFETs”, Nanotechnology, IEEE Transactions, Volume 5, Issue 3, May 2006, Page(s):186 – 191.
[26] User’s Manual, ISE-TCAD, 2004.
[27] Frescura, B.L.; Rusert, R.; Schroeder, J.; “Mesa isolation — An isolation technique for integrated circuits”, Electron Devices Meeting, 1966 International, Volume 12, 1966, Page(s):66 – 68.
[28] Jeon, D.-S.; Burk, D.E.; “A temperature-dependent SOI MOSFET model for high-temperature application (27 °C-300 °C)”, Electron Devices, IEEE Transactions on, Volume 38, Issue 9, Sept. 1991, Page(s):2101 – 2111
[29] Barsan, R.M.; Van De Wiele, F.; “Subthreshold behavior and threshold voltages of short-channel dual-gate MOSFETs”, Solid-State Circuits, IEEE Journal, Volume 17, Issue 3, Jun 1982, Page(s):626 – 635.
[30] Matsumoto, T.; Maeda, S.; Hirano, Y.; Eikyu, K.; Yamaguchi, Y.; Maegawa, S.; Inuishi, M.; Nishimura, T.; “Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 μm partially depleted SOI MOSFETs”, Electron Devices, IEEE Transactions, Volume 49, Issue 1, Jan. 2002, Page(s):55 - 60
[31] Chen, Y.; Madathil, S.N.E.; Clough, F.J.; Milne, W.I.; “The influence of lattice temperature on SOI MOSFET's output characteristics”, Physical Modelling of Semiconductor Devices, IEE Colloquium, 3 Apr 1995, Page(s):8/1 - 8/4,
[32] Hisamoto, D.; Wen-Chin Lee; Kedzierski, J.; Anderson, E.; Takeuchi, H.; Asano, K.; Tsu-Jae King; Bokor, J.; Chenming Hu, “A folded-channel MOSFET for deep-sub-tenth micron era”, Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International, 6-9 Dec. 1998, Page(s):1032 – 1034.
[33] Lindert, N.; Yang-Kyu Choi; Leland Chang; Anderson, E.; Wenchin Lee; Tsu-Jae King; Bokor, J.; Chenming Hu, “Quasi-planar NMOS FinFETs with sub-100 nm gate lengths”, Device Research Conference, 25-27 June 2001, Page(s):26 – 27.
[34] Fung, S.K.H.; Man Kit Wong; Chan, M.; Nguyen, C.T.; Ko, P.K.; “Frequency dispersion in partially depleted SOI MOSFET output resistance”, SOI Conference, 1996. Proceedings., 1996 IEEE International, 30 Sept.-3 Oct. 1996, Page(s):146 – 147.
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