在即時動態場景的光線追蹤研究中，一個重要的議題即如何快速的建構出物件分群結構。本論文提出了一個基於surface-area-heuristic (SAH)指標之低成本binned bounding volume hierarchy (BVH) 樹結構建構電路設計。此樹結構建構電路的主要 工作是將一個節點內所包含的三角形根據給定的分割位置分成兩群三角形，並建構出兩個子節點紀錄三角形分群的結果。子節點建構的同時也會決定其分割位置以進行下一個節點的分群工作。
本論文一開始提出一個dual-bank的三角形記憶體架構，其透過少許數量的輔助暫存空間以及特殊的記憶體讀寫排程演算法來提升記憶體空間使用率。整體的記憶體使用量，與傳統的ping-pong緩衝記憶體架構比較，只需要其一半的暫存記憶體空間。接下來，一個管線化二元搜尋電路模組則用於決定輸出的三角形要分類至哪一個分類盒(bin)內。當所有的三角形皆被掃描過並更新至分類盒後，每個分類盒的axis-aligned bounding box (AABB)以及包含的三角形數量會開始進行組合，以計算出每一個分割候選位置的SAH成本。整個SAH計算僅花費102個時間週期。為了要提升硬體使用率，本篇提出了一個雙子樹交織(dual subtree interleaving)的排程方式進行節點分割工作。其使用兩個堆疊來實現，並維持兩個堆疊內都有尚未完成的子樹可以進行節點分割工作。
本篇提出的BVH樹結構建構電路硬體成本僅約361K個閘，並且在90nm製程下可以運行至199MHz工作時脈。與先前的設計比較，其面積時間乘積比值可以達到約原本的0.74。本篇之設計貢獻在於嵌入式環境下的即時動態場景光線追蹤系統開發。

The acceleration of tree construction is a very important issue for real-time ray-tracing
of dynamic scenes. This paper presents a low-cost design of bounding volume hierarchy (BVH) tree builder based on surface-area-heuristic (SAH) binned BVH algorithm. The core operation of the tree builder is to partition one node of primitives into two separate parts as their child nodes, and also determine the next split location for two new born nodes.
This paper first proposes an efficient dual-bank primitive buffer architecture. With the
help of little extra auxiliary buffer space and the proposed special buffer access algorithm, our design can save one half of buffer capacity compared with the traditional ping-pong buffer design. Next, a pipeline binary search module has also been proposed to efficiently determine the bin location of the incoming primitive. After all the primitives have been scanned, the primitive count and axis-aligned bounding box (AABB) of each individual bin have to be combined in order to find the SAH cost of each split candidate. By considering the bin combination computation of all the split candidates, an efficient bin combine unit can be developed by simply accumulating the incoming bin data. The total number of cycles required in SAH calculation process is only 102. In order to increase the hardware utilization, this paper also proposed a dual subtree interleaving approach which interleaves the node-split operations from two stacks, and there is always a subtree is built in
each stack.
The proposed treebuilder only costs about 358K gates, and can run up to 141MHz for
90nm technology. Our area-time-product performance can achieve about 0.74 comparing to previous works. The proposed design can contribute to the development of embedded real-time ray-tracing systems.

論文審定書 i
摘要 ii
Abstract iii
圖目錄 vi
表目錄 vii
第一章概論 1
1.1 研究動機 1
1.2 論文大綱 3
第二章背景知識與相關研究 4
2.1 光線追蹤 4
2.2 Bounding Volume Hierarchy (BVH) 5
2.3 Surface Area Heuristic 8
2.4 相關BVH結構與變形 8
2.5 BVH建構加速 11
第三章Binned BVH建構電路設計 12
3.1 整體電路架構 12
3.2 邊界產生單元(Border Generation Unit) 15
3.3 三角形分群單元(Partition Unit) 16
3.3.1 三角形分群工作 17
3.3.2 三角形分群單元電路架構 21
3.3.3 Dual Primitive Buffer讀寫排程 23
3.4 分類選擇單元(Bin-Decision Unit) 30
3.5 分類組合單元(Bin Combine Unit) 31
3.6 SAH計算單元與SAH比較單元 34
3.7 多緒執行與工作分配單元 36
第四章實作結果與實驗比較 40
第五章結論與未來目標 49
參考文獻 51
附錄A 三角形分群排程控制虛擬碼 54

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