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博碩士論文 etd-0627115-101740 詳細資訊
Title page for etd-0627115-101740
論文名稱
Title
新式體效應電阻式記憶體與降低成形電壓之研究
Study on the Bulk Oxygen Effect and Reducing Forming Voltage in a Novel Resistance Random Access Memory
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
103
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2015-07-08
繳交日期
Date of Submission
2015-08-10
關鍵字
Keywords
成形限制電流、電阻式記憶體、氧化鎵摻雜之銦錫氧化物、體效應氧離子傳導機制、成形電壓、低介電係數氧化層
RRAM, forming voltage, forming current compliance, Indium tin oxide doped gallium oxide, low dielectric oxide layer, bulk effect oxygen conduction
統計
Statistics
本論文已被瀏覽 5688 次,被下載 92
The thesis/dissertation has been browsed 5688 times, has been downloaded 92 times.
中文摘要
隨著科技的演進,記憶體的使用越來越頻繁,其中重要性也越來越受到重視,電阻式記憶體(Resistance Random Access Memory)是現今學術界及工業界主要研究的次世代非揮發性記憶體其中之一,而且電阻式記憶體的成形行為和傳導機制,一直是學術界及工業界積極想研究的課題,所以,本論文主要是對電阻式記憶體的成形行為和傳導機制做研究。
電阻式記憶體的成形電壓,是元件產生崩潰所引起的,而低成形電壓,能使元件在串聯電晶體操作時,使電晶體不會因為成形電壓過大而損壞,所以,本研究在元件引入一層低介電係數的氧化層,並利用低介電係數/高介電係數的元件堆疊方式,來研究此結構對成形電壓之影響,而研究結果,確實能有效使元件的成形電壓下降。
本研究以物理濺鍍方式沉積氧化鎵摻雜之銦錫氧化物薄膜,製作ITO/Ga2O3:ITO/TiN結構的電阻式記憶體元件,並設置不同的成形限制電流,再對元件做set和reset操作,發現元件會隨著成形的限制電流不同,而有趨緩和急遽的set和reset,接著再利用電流機制擬合進行電壓及電流分析,並提出模型對此現象做解釋。
隨著溫度的變化,氧離子會有移動的情形,之後對ITO/Ga2O3:ITO/TiN元件做升溫實驗,實驗結果隨著溫度上升,操作電流會有上升的趨勢,接著再利用電流機制擬合進行電壓及電流分析,並提出模型對此現象做解釋。
由前幾章實驗發現,ITO/Ga2O3:ITO/TiN元件為體效應的氧離子傳導機制,所以利用在元件上加鍍Pt電極,並比較不同厚度的ITO上電極的元件特性,來驗證此傳導機制。
Abstract
With the evolution of technology, the use of the memory is more and more frequent, so that it’s importance catches more and more attention. RRAM (resistance random access memory) is the one of the major academic and industrial research on the next-generation non-volatile memory. Moreover, the forming process of RRAM is also the major topic in the academia and industrial world. Therefore, the forming behavior and the conduction mechanism are the mainly subjects in this study.
The forming voltage is the key to make the device soft breakdown, and low forming voltage can prevent the device from damaging when connecting with the transistors. Therefore, in this study, the findings show that inserting a low dielectric oxide layer and using the structure of the low dielectric layer/the high dielectric layer surely reduce the forming voltage.
The Indium tin oxide doped gallium oxide thin film was prepared by RF sputtering, and it was fabricated the RRAM with ITO/Ga2O3:ITO/TiN structure. With setting the different forming current compliance and operating the device, the findings show that there are the slower and sharp set and reset process. Based on the corroboration of conduction current fitting analysis, a model was proposed to explain the electrical resistive switching behaviors.
When the temperature changes, oxygen ions will move. As a result, doing experiment on ITO/Ga2O3:ITO/TiN with the different temperature, the findings show that the operating current will show the same result with the temperature rising up. Based on the corroboration of conduction current fitting analysis, a model was proposed to explain the electrical resistive switching behaviors.
From the former chapters, RRAM of ITO/Ga2O3:ITO/TiN has bulk effect oxygen conduction mechanism. Therefore, to prove this conduction mechanism, we prepare platinum thin film on ITO/Ga2O3:ITO/TiN by RF sputtering and compare the characteristic of the device with the different Indium tin oxide thickness.
目次 Table of Contents
[致謝+i]
[中文摘要+ii]
[Abstract+iii]
[目錄+v]
[圖目錄+ix]
[表目錄+xiii]
[第一章 緒論+1]
[1-1 前言+1]
[1-2 研究目的與動機+2]
[第二章 文獻回顧+3]
[2-1 記憶體簡介+3]
[2-2 次世代非揮發性記憶體+3]
[2-2-1 鐵電式記憶體(FeRAM)+4]
[2-2-2 磁阻式記憶體(MRAM)+5]
[2-2-3 相變化記憶體(PCRAM)+6]
[2-2-4 電阻式記憶體(RRAM)+7]
[2-3 電阻式記憶體切換機制+10]
[2-3-1 阻絲理論(Filament theory)+10]
[2-3-2 介面效應(Filament theory)+10]
[2-4 絕緣體載子傳導機制+12]
[2-4-1 歐姆傳導(Ohmic Conduction)+13]
[2-4-2 蕭基發射(Schottky emission)+14]
[2-4-3 普爾-法蘭克發射(Poole-Frenkel emission)+15]
[2-4-4 跳躍傳導(Hopping Conduction)+16]
[2-4-5 穿隧(Tunneling)+17]
[2-4-6 空間電荷限制電流(Space Charge Limited Current, SCLC)+18]
[第三章 實驗設備介紹+19]
[3-1 製程設備+19]
[3-1-1 多靶磁控濺鍍系統(Multi-Target Sputter)+19]
[3-2 材料分析設備+20]
[3-2-1 傅立葉轉換紅外光譜儀(Fourier-Transform Infrared Spectrometer)+20]
[3-2-2 X光電子能譜儀(X-ray Photoelectron Spectroscopy)+22]
[3-2-3 N&K薄膜特性分析儀(N & K analyzer)+23]
[3-3 電性量測設備+24]
[3-3-1 半導體精準電性量測系統+24]
[第四章 引入低介電系數氧化層對RRAM成形電壓影響之研究+26]
[4-1 實驗動機+26]
[4-2 元件製作流程+26]
[4-2-1 鉿氧化物薄膜備製+27]
[4-2-2 硼氮氧化物薄膜備製+28]
[4-2-3 白金上電極備製+29]
[4-3 薄膜材料分析+29]
[4-3-1 FTIR化學定性分析+29]
[4-3-2 XPS化學定量分析+30]
[4-4 元件基本特性+31]
[4-4-1 Pt/HfO2/TiN元件基本特性+31]
[4-4-2 Pt/BNO/HfO2/TiN元件基本特性+33]
[4-4-3 記憶保存力(Retention)+34]
[4-4-4 耐操度(Endurance)+35]
[4-4-5 Pt/BNO/HfO2/TiN和Pt/HfO2/TiN成形電壓比較+36]
[4-4-6 COMSOL模型模擬+38]
[4-4-7 模型建立+40]
[第五章 成形限流對氧化鎵摻雜之銦錫氧化物電阻式記憶體影響之研究+42]
[5-1 實驗動機+42]
[5-2 元件製作流程+43]
[5-2-1 氧化鎵摻雜銦錫氧化物薄膜製備+44]
[5-2-2 銦錫氧化物上電極製備+45]
[5-3 薄膜材料分析+45]
[5-3-1 FTIR化學定性分析+46]
[5-3-2 XPS化學定量分析+46]
[5-4 元件基本特性+47]
[5-4-1 不同尺寸元件操作I-V特性比較+49]
[5-4-2 不同成形限流下操作I-V特性比較+50]
[5-4-3 模型建立+54]
[第六章 溫度變化對氧化鎵摻雜之銦錫氧化物電阻式記憶體影響之研究+57]
[6-1 不同成形限流下元件的記憶保存力+57]
[6-1-1 元件傳導機制研究+59]
[6-2 不同溫度對元件操作I-V特性比較+60]
[6-3 升溫和未升溫元件比較+65]
[6-4 模型建立+67]
[第七章 不同銦錫氧化物電極厚度對氧化鎵摻雜之銦錫氧化物電阻式記憶體影響之研究+69]
[7-1 實驗動機+69]
[7-2 元件製作流程+69]
[7-2-1 銦錫氧化物上電極製備+70]
[7-2-2 白金備製+71]
[7-3 不同成形限流下操作I-V特性比較+72]
[7-4 不同厚度ITO上電極I-V特性比較+74]
[7-5 模型建立+76]
[第八章 結論+80]
[參考文獻+82]
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