隨著智慧時代的來臨，現今社會智慧型手機已經是每個人必備的工具，隨著智慧手機熱，較高階的手機追求高的解析度，而低溫複晶矽(LTPS)薄膜電晶體具有高載子遷移率所以低溫複晶矽薄膜電晶體又開始被拿出來重新研究，還有近年來，顯示器朝著大尺寸發展，而非晶態銦鎵鋅氧(InGaZnO)薄膜電晶體具有良好的均勻度、高載子遷移率和較低的製程溫度等眾多優點所以是現今的熱門研究題目。
本研究主要是對LTPS薄膜電晶體與a-IGZO薄膜電晶體，兩者在熱載子效應與自熱效應下的劣化機制去做探討，一開始先討論LTPS薄膜電晶體在Normal type結構與GOLD (Gate overlapped lightly doped drain)結構下的兩者的電性比較，可以發現在GOLD結構因為Gate覆蓋面積較大，並且覆蓋到Lightly doped drain(LDD)，所以Gate可以控制LDD區域，導致在操作時GOLD結構的特性比Normal type來的好，為了研究GOLD結構於電流操作下的可靠度行為，下一章節討論NMOS LTPS-TFTs在GOLD結構下的熱載子效應/自熱效應的劣化機制，皆發現無論是熱載子效應還是自熱效應的可靠度實驗，隨著Gate端施加越大的電壓元件劣化越嚴重，並且劣化的行為一致，在同為自熱效應的可靠度條件下，將元件寬度(width)越大的元件Vt、S.S與gm的劣化越嚴重，這是一個典型的自熱效應下所產生的劣化，因此認為GOLD結構下的熱載子效應與自熱效應所顯現出來的劣化皆為大電流的操作所產生的自熱現象所造成的；並且研究發現GI層的SiNx厚度改變下，會有不同劣化現象出現，除了電子會因為熱場發射注入到前介電層(SiOx)，另外SiNx層越厚則會出現越嚴重的電洞從閘極端注入到後介電層(SiNx)的現象，使得元件的起始電壓會有嚴重的不穩定性。
下一個章節，研究PMOS LTPS-TFTs在閘極負電壓並且升溫(Negative Gate Bias Temperature Instability, NBTI)的可靠度行為，發現劣化的現象與傳統的NBTI非常不同，經過可靠度後電晶體的on-current反而增加，推測是金屬閘極兩端的強電場造成電子反向從金屬閘極注入到後介面層(SiNx)，使得電晶體的有效通道長度減少增加on-current。
最後討論a-IGZO薄膜電晶體在熱載子效應與自熱效應兩者的劣化機制，操作上分別將固定汲極電壓改變閘極與固定閘極電壓改變汲極電壓去做比較，發現經過兩種操作方式後，電流的劣化都是局部的on-state current劣化，此劣化行為會因撞擊汲極端區域的電子數目的增加與橫向電場的增加而變嚴重；另一部分的實驗討論a-IGZO薄膜電晶體於自熱效應下的劣化行為，將實驗條件固定在相同的閘極電壓下，改變汲極電壓，經過可靠度測試後量測發現有飽和區反掃有嚴重的VT飄移，並且也出現on-state電流的局部劣化，換句話說就是熱載子實驗發生的劣化機制也發生在此自熱效應的實驗條件中，而在飽和區反掃量測下起始電壓會有嚴重的劣化是因為操作在self-heating stress時元件通道會產生大量的熱，造成電子更容易注入到閘極絕緣層中。
關鍵字:薄膜電晶體、銦鎵鋅氧、熱載子效應、自熱效應、臨界電壓、銳角效應、電荷捕獲

With the arrival of wisdom of the ages, smart phones have been already essential necessary for everyone in the present day. Due to the requirement of high resolution for smart phones, Low-Temperature Polycrystalline-Silicon (LTPS) thin film transistors have been restudied again owing to its higher carrier mobility. Furthermore, the displays also turn towards large-scale development in the resent years. Since amorphous idium-gallium-zinc-oxide (InGaZnO) TFT possesses lots of advantages, such as better uniformity, higher carrier mobility and lower process temperature, it becomes to a popular research topic.
This study focuses on the hot-carrier and self-heating effects in LTPS-TFTs and a-IGZO TFTs. First, the comparison of normal type and GOLD (Gate overlapped lightly doped drain) structures are carried out. It is found that the GOLD structure has a better electrical characteristic than that of normal type due to higher coverage area of metal gate. In order to investigate the reliability of current operation for GOLD structure, the effects on hot-carrier and self-heating stress are discussed in the next section. Accoring to results, it is found that the degree of degradation becomes more severe as gate bias increases regardless of hot-carrier and self-heating stresses. However, the degradation behaviors after hot-carrier and self-heating stresses are consisten with each other. These degradations are further found to depend on device width, representing that they are belonged to a classical self-heating-induced degradation behaviors. Therefore, these instabilities after hot-carrier and self-heating stresses can be both attributed to the high channel current operation-induced self-heating effect. Furthermore, the degradation behaviors become to be dominated by another mechanism as the SiNx thickness of gate insulator increases. Except the electron-trapping into the SiOx layer through thermonionic-field emission, the phenomenon about hole-injection becomes to more serious in thicker SiNx thickness of gate insulator devices, resulting in the instability of threshold voltage becomes more severe.
In the final section, hot-carrier effects and self-heating effects in a-IGZO TFTs are also well discussed. Under hot-carrier stress, devices were electrically stressed by different drain voltages at fixed gate voltage and different gate voltages at fixed drain voltage. Both these two kinds of stresses show on-current degradation as gate and drain biases of stresses increases, hence, it can be considered that the degradation behaviors are related to both increase of channel electrons and lateral electric field in the channel.
On the other hand, we focus on degradation behaviors of self-heating effects in a-IGZO TFTs. Devices were stressed by different drain voltages at fixed gate voltage and all the drain voltage are less than gate voltage. After the series of stresses, both threshold voltage shift and on-current degradation can be observed under source and drain interchange mode. Accordingly, it is indicated that the degraded mechanisms of hot-carrier-induced trap state generation had been also occured in that of self-heating stress. However, the additional VT-shift might be attributed to higher channel current-induced Joule-heating generation near the drain side during self-heating stress. Because the charge-trapping effect is a thermionic-field emission process, the higher channel temperature enhanced more electrons trapped into the gate insulator and induced extra VT-shift under source/drain interchange mode.
Keyword: Thin Film Transistor, InGaZnO, Hot-Carrier Effect, Self-Heating Effect, Threshold voltage, Corner Effect, charge trapping.

目錄
誌謝 ii
摘要 iv
Abstract vi
目錄 viii
圖次 ix
第一章 序論 1
1.1研究背景 1
1.2主動層材料性質與優劣比較 2
1.3為何選擇LTPS與a-IGZO? 3
1.4研究動機 4
第二章 參數萃取與儀器介紹 9
2.1參數萃取 9
2.1.1電流與載子遷移率 9
2.1.2 臨界電壓(VT) 10
2.1.3 次臨界擺幅 (Subthreshold swing, S.S.) 11
2.2 儀器介紹 12
第三章 GOLD和normal-type結構下之物理機制與電性分析 15
3.1簡介 15
3.2實驗架構 16
3.3 結果與討論 17
3.3.1 GOLD和normal-type結構下的電性分析 17
3.3.2 GOLD結構之熱載子效應與自熱載子效應的研究 21
3.3.3 GOLD結構在GI厚度不同的影響 24
3.3.4 P-type時GOLD結構在NBTI下之影響 28
3.4.總結 30
第四章 Etch-stop layer結構下之物理機制與電性分析 67
4.1簡介 67
4.2實驗架構 68
4.3實驗結果與討論 69
4.3.1 Etch-stop layer結構之熱載子效應的研究 69
4.3.2 Etch-stop layer結構之自熱效應的研究 71
4.4總結 74
第五章 結論 87
References 88

[1] Park, Joon Seok, et al. "Review of recent developments in amorphous oxide semiconductor thin-film transistor devices." Thin Solid Films 520.6 (2012): 1679-1693.
[2] Huang, Sheng-Yao, et al. "Thermal Effect on the Gate-Drain Bias Stress for Amorphous InGaZnO Thin Film Transistors." Electrochemical and Solid-State Letters 15.5 (2012): H161-H163.
[3] Kamiya, Toshio, and Hideo Hosono. "Material characteristics and applications of transparent amorphous oxide semiconductors." NPG Asia Materials 2.1 (2010): 15-22.
[4] Park, Joon Seok, et al. "The effect of UV-assisted cleaning on the performance and stability of amorphous oxide semiconductor thin-film transistors under illumination." Applied Physics Letters 98.1 (2011): 012107.
[5] Oh, Himchan, et al. "Enhanced bias illumination stability of oxide thin film transistor through insertion of ultrathin positive charge barrier into active material." Applied Physics Letters 99.2 (2011): 022105.
[6] Ahn, Seung‐Eon, et al. "Metal oxide thin film phototransistor for remote touch interactive displays." Advanced Materials 24.19 (2012): 2631-2636.
[7] Kwon, Jang-Yeon, et al. "The impact of gate dielectric materials on the light-induced bias instability in Hf-In-Zn-O thin film transistor." Applied Physics Letters 97.18 (2010): 183503.
[8] Chen, Te-Chih, et al. "Behaviors of InGaZnO thin film transistor under illuminated positive gate-bias stress." Applied Physics Letters 97.11 (2010): 112104.
[9] Liu, Po-Tsun, Yi-Teh Chou, and Li-Feng Teng. "Environment-dependent metastability of passivation-free indium zinc oxide thin film transistor after gate bias stress." Applied Physics Letters 95.23 (2009): 233504.
[10] Chung, Wan-Fang, et al. "Environment-dependent thermal instability of sol-gel derived amorphous indium-gallium-zinc-oxide thin film transistors." Applied Physics Letters 98.15 (2011).
[11] Su, Lisa T., et al. "Measurement and modeling of self-heating in SOI nMOSFET's." Electron Devices, IEEE Transactions on 41.1 (1994): 69-75.
[12] Valletta, Antonio, et al. "Self-heating effects in polycrystalline silicon thin film transistors." Applied Physics Letters 89.9 (2006): 093509.
[13] Jeong, Jae Kyeong, et al. "Origin of threshold voltage instability in indium-gallium-zinc oxide thin film transistors." Applied Physics Letters 93.12 (2008): 123508.
[14] Lin, Horng-Chih, Kai-Hsiang Chang, and Tiao-Yuan Huang. "Characterization of AC Hot-Carrier Effects in Poly-Si Thin-Film Transistors." Electron Devices, IEEE Transactions on 56.11 (2009): 2664-2669.
[15] Uraoka, Yukiharu, et al. "Hot carrier effects in low-temperature polysilicon thin-film transistors." Japanese Journal of Applied Physics 40.4S (2001): 2833.
[16] Toyota, Yoshiaki, Takeo Shiba, and Makoto Ohkura. "Effects of the timing of AC stress on device degradation produced by trap states in low-temperature polycrystalline-silicon TFTs." Electron Devices, IEEE Transactions on 52.8 (2005): 1766-1771.
[17] Cho, In-Tak, et al. "Charge trapping and detrapping characteristics in amorphous InGaZnO TFTs under static and dynamic stresses." Semiconductor Science and Technology 24.1 (2009): 015013.
[18] Tsai, Ming-Yen, et al. "Investigating the degradation behavior under hot carrier stress for InGaZnO TFTs with symmetric and asymmetric structures." Thin Solid Films 528 (2013): 57-60.
[19] Moon, Kook Chul, Jae-Hoon Lee, and Min-Koo Han. "The study of hot-carrier stress on poly-Si TFT employing CV measurement." Electron Devices, IEEE Transactions on 52.4 (2005): 512-517.
[20] Inoue, Satoshi, Hiroyuki Ohshima, and Tatsuya Shimoda. "Analysis of degradation phenomenon caused by self-heating in low-temperature-processed polycrystalline silicon thin film transistors." Japanese Journal of Applied Physics 41.11R (2002): 6313.
[21] Hsieh, Tien-Yu, et al. "Systematic Investigations on Self-Heating-Effect-Induced Degradation Behavior in a-InGaZnO Thin-Film Transistors." Electron Devices, IEEE Transactions on 59.12 (2012): 3389-3395.
[22] Mourey, Devin, et al. "Thermal effects in oxide Tf T s." Device Research Conference (DRC), 2010. IEEE, 2010.
[23] Tai, Ya-Hsiang, Shih Che Huang, and Hao Lin Chiu. "Degradation of capacitance-voltage characteristics induced by self-heating effect in poly-Si TFTs." Electrochemical and Solid-State Letters 9.6 (2006): G208-G210.
[24] Toyota, Yoshiaki, Takeo Shiba, and Makoto Ohkura. "A new model for device degradation in low-temperature N-channel polycrystalline silicon TFTs under AC stress." Electron Devices, IEEE Transactions on 51.6 (2004): 927-933.
[25] Chen, Te-Chih, et al. "Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor." Applied Physics Letters 99.2 (2011): 022104.
[26] Liao, J. C., et al. "Dynamic negative bias temperature instability (NBTI) of low-temperature polycrystalline silicon (LTPS) thin-film transistors." Electron Device Letters, IEEE 29.5 (2008): 477-479.
[27] Lin, Chia-Sheng, et al. "NBTI degradation in LTPS TFTs under mechanical tensile strain." Electron Device Letters, IEEE 32.7 (2011): 907-909.
[28] Parke, Stephen, et al. "Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model." Electron Devices, IEEE Transactions on 39.7 (1992): 1694-1703.
[30] Toyota, Yoshiaki, Takeo Shiba, and Makoto Ohkura. "Effects of the timing of AC stress on device degradation produced by trap states in low-temperature polycrystalline-silicon TFTs." Electron Devices, IEEE Transactions on 52.8 (2005): 1766-1771.
[31] Fuyuki, Takashi, et al. "Thermal degradation of low temperature poly-Si TFT." Thin Solid Films 487.1 (2005): 216-220.
[32] Takechi, Kazushige, et al. "Dependence of self-heating effects on operation conditions and device structures for polycrystalline silicon TFTs." Electron Devices, IEEE Transactions on 53.2 (2006): 251-257.
[33] Fujii, Mami, et al. "Thermal analysis of degradation in Ga2O3–In2O3–ZnO thin-film transistors." Japanese Journal of Applied Physics 47.8R (2008): 6236.
[34] Urakawa, Satoshi, et al. "Thermal analysis of amorphous oxide thin-film transistor degraded by combination of joule heating and hot carrier effect." Applied Physics Letters 102.5 (2013): 053506.
[35] Lin, Chia-Sheng, et al. "Anomalous on-current and subthreshold swing improvement in low-temperature polycrystalline-silicon thin-film transistors under Gate bias stress." Applied Physics Letters 98.12 (2011): 122101.
[36] Lin, Chia-Sheng, et al. "Anomalous on-current and subthreshold swing improvement in low-temperature polycrystalline-silicon thin-film transistors under Gate bias stress." Applied Physics Letters 98.12 (2011): 122101.
[37] De Wang, Shen, et al. "Drain/gate-voltage-dependent on-current and off-current instabilities in polycrystalline silicon thin-film transistors under electrical stress." Japanese Journal of Applied Physics 44.9R (2005): 6435.