本文提出了一種可應用於穿戴式醫療系統中可以抑制生醫訊號中的市電電源干擾並且可調整截止頻率的濾波器，該類比前端電路採用的是TSMC 180奈米製程，是一個可程式化的設計，可以結合系統中的PLL產生所需的時脈。此物聯網系統的目標是將類比及數位結合起來設計成一個客製化SOC晶片，為了將此系統設計為可攜式，此系統整合晶片必須低耗電、小面積。在皮膚表面量測到的訊號強度非常微弱，並且容易受到干擾，尤其是市電電源的干擾。為了消除市電電源干擾，我們使用切換式電容電路設計了一個截止頻率在50Hz或60Hz的濾波器並且具有高品質因素的陷波濾波器，此濾波器的截止頻率可針對不同國家透過調整外部輸入的時脈來進行調整。當選擇二階濾波器時品質因素的量測結果可以達到20，而四階濾波器為12.5。雖然四階濾波器的品質因素較低，但有更高的衰減率。二階濾波器的所消耗的電流為13.3微安培(方均根)，四階濾波器為27微安培(方均根)。

This thesis presents an adjustable filter which can reject the main interference in a wearable health care system. This AFE system is implemented in TSMC 180nm process, and it is a programable system which is combined with a PLL circuit for clock generation. The target of the IoT system is to build a custom SOC chip that consists of analog and digital system. To make it wearable, this SOC chip should have low power, and small area. The signal measured on the surface of skin is very low in strength and vulnerable to noise, especially for the main interference. To eliminate the interference, we use switched capacitor circuit to design a high Q notch filter, and the notch frequency is 50 Hz or 60 Hz. The notch frequency of this filter is adjustable for different countries, it can be determined by the speed of an externally supplied clock signal. The measured result of Q factor is 20 for the second order notch, and 12.5 for fourth order notch. Although the fourth order filter has smaller Q factor, it has larger attenuation depth. The current consumed by the second order notch is 13.3mu A (rms current) and the fourth order notch is 27mu A (rms current).

論文摘要 i
ABSTRACT ii
CONSTENTS iii
LIST OF FIGURES v
LIST OF TABLES ix
Chapter 1 Introduction 1
1.1 Background of this thesis 2
1.2 Organization 4
Chapter 2 The Switched Capacitor Bi-quad Filters which can reduce the power line interference on bionic signal 5
2.1 The Classification of Signal 5
2.2 The Second-order RC Bi-quad notch filters 6
2.2.1 Basic theorem of Notch Filter 6
2.2.2 The transfer function of a second order main interference rejection filter 8
2.2.3 Two-integrator Bi-quad Notch Filter 9
2.3 The Switched Capacitor Circuits 12
2.3.1 The resistor emulation of switched capacitor circuit 12
2.3.2 Switched Capacitor integrator 16
2.3.3 Non-ideal model of switch 20
2.3.4 Thermal noise in switched capacitor circuits 28
2.3.5 Spectra of switched capacitor filters 30
2.4 CMOS operational amplifier 31
2.4.1 Small signal model of operational amplifier 32
2.4.2 Compensation for the AMP 34
Chapter 3 Circuit design to implement the Switched Capacitor Bi-quad Filters 40
3.1 Performance of proposed notch filter 40
3.2 Non-overlap clock generation circuit 42
3.3 Design of 2 stage CMOS Operational Amplifier 44
3.3.1 Structure of two stage CMOS AMP 45
3.3.2 Design of the CMOS OPA 47
3.3.3 Frequency response of the operational amplifier 51
3.3.4 Compensation for the AMP 52
3.4 Design of Switched Capacitor Notch Filter 54
3.4.1 The clock frequency of this SC notch 56
3.4.2 Frequency response 56
3.4.3 Transient analysis 58
3.4.4 Power dissipation 61
3.4.5 Sensitivity of switched capacitor circuit 62
3.5 The design of fourth order notch filter 64
Chapter 4 Measured results 66
4.1 The setup of testing environment 66
4.2 Frequency Response 68
4.2.1 Second order notch filter 69
4.2.2 Frequency response of fourth order notch filter 71
4.3 Measurement of input range 72
4.4 Measured result of power dissipation 73
4.5 The reduction of power line interference on ExG signal detecting system 74
4.6 The total harmonic distortion 75
4.7 Output Noise 76
4.8 Comparison of this filter and existed filters 77
Chapter 5 Conclusion and future work 78
5.1 Conclusion 78
5.2 Future work 79
Reference 81

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