由於無線通訊技術的發達，使得現今電磁環境日益複雜，加上電子電路朝向高速低電壓化及小型化發展，使得電路系統電磁耐受度(EMS)的重要性與日俱增。本論文將從兩個方向了解及解決電路系統對於電磁耐受的技術，一為電磁耐受量測環境建立及均勻場校準方法的研究，由建立的量測環境去驗證電路系統的硬體設計與其電磁耐受特性的相關性。第二部分為理論分析模型的建立及探討，藉由時域有限差分法(FDTD)及有限元素法(FEM)的理論模擬，驗證所建立的量測及模擬技術彼此的準確性。並對於電路佈局中的不同信號走線方式作探討，分析電源供應平面(PDN)電磁耐受的理論及機制，此外亦提出各種不同改善電磁耐受度之設計，並提出極為有效之週期性電磁能隙結構(EBG)來改善電源供應平面電磁耐受的問題。最後提出以屏蔽概念之設計觀念來抗電磁干擾以提升信號品質。

With the enormously developing of the wireless communication technology, the electromagnetic environment exposing to the electrical devices is becoming more and more complex. Besides, the trends of designing high-speed digital computer systems are toward fast edge rates, high clock frequencies, and low voltage levels. The electromagnetic susceptibility (EMS) or immunity of the high-speed circuit has become an important issue today apparently. In this thesis, we will firstly establish the measurement environment and calibration technology for numerical validation. Then we employ the three-dimension finite-differential time-domain (3D-FDTD) numerical method compared to the finite element method (FEM) to simulate the EMS behavior of the power delivery network (PDN) and traces of the printed circuit boards (PCB). In addition to several types of layout of the traces studied in this thesis, we also explain the mechanism and phenomenon of the EMS of the power/ground planes of the PCB. Besides the EMS behavior research of the traditional solutions to suppress the power noise, we propose an electromagnetic bandgap structure (EBG) which has the broadband suppression of the power noise and is validated to be effective to improve the EMS problems. Finally, we also propose a novel concept to increase the signal integrity (SI) by shielding design.

論文摘要 i
目錄 ii
圖表目錄 v
第一章 序論 1
1.1 研究背景及動機 1
1.2研究方法及大綱 2
1.3 章節摘要 2
第二章 FDTD演算法 4
2.1 Yee網格配置及離散化公式 4
2.2 穩定準則 8
2.3 吸收邊界 8
2.4 集總元件 10
2.4.1 電阻 12
2.4.2 電容 12
2.4.3 電感 13
2.5 全場散射場 13
第三章 電子電路的電磁耐受性研究之簡介與規範 24
3.1 電磁耐受之簡介 24
3.2 電磁耐受之測試規範 24
3.2.1 參考IEC61000-4-3建立之量測環境 24
3.2.2 均勻場強之校正 27
3.2.3 待測物測試設置 29
第四章 信號走線設計之電磁耐受(EMS)分析探討 32
4.1傳輸線電磁耐受理論分析 32
4.2 單根傳輸線 36
4.3單根傳輸線之不連續特性探討 39
4.3.1 彎角 40
4.3.2 過槽孔 43
4.4差動傳輸線 51
第五章 電源供應平面(PDN)電磁耐受之分析探討 57
5.1 接地彈跳現象及原因與電磁耐受之關係 57
5.2 模擬EMS之方法及現象探討 62
5.3 常見之接地彈跳雜訊防治對策對EMS之影響 67
5.3.1 去耦合電容 67
5.3.2 矩形狹縫連結通道之設計 72
5.4 電磁能隙結構於電源供應平面之應用與特性 78
5.5 電磁能隙結構於電源供應平面之EMS影響 81
第六章 以電磁屏蔽概念之信號耐受設計 92
6.1 簡介 92
6.2 以電磁屏蔽之信號設計探討 93
6.3 討論 109
第七章 結論 111
參考文獻 112

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