在現今高速數位電路中，因其信號上升時間和下降時間為兆分之ㄧ秒，電路中的電源平面可以被考慮為一動態電磁場。因數位邏輯的切換而產生的瞬間電流變化，會在電源平面間產生同步切換雜訊或接地彈跳雜訊，而造成電路設計中信號完整性和電源完整性的問題。為了實現系統級的電源完整性模擬，我們用集總元件模型去電源平面的共振效應，並結合電路模擬器，例如SPICE。
因此我們使用二維傳輸線方法去建立電源平面的集總元件模型，且應用此模型可以有效地分析高速電源系統中的接地彈跳雜訊，此系統為一BGA封裝結構設置在PCB上。我們發現此系統的雜訊現象和單純考慮封裝結構時有很大的不同。接下來我們並結合電源平面模型和去耦合電容快速模擬對抑制接地雜訊的影響。由實驗的量測結果，我們也驗證了此方法的準確性。
在電源與接地面間加去耦合電容以抑制GBN為一般常見的作法，但一般來講由於引腳的電感性使電容在GHz以上便失去抑制效果。最近有一個新方法被提出，是應用電磁能隙結構所造成的high impedance surface去抑制高頻接地彈跳雜訊。最後我們使用二維傳輸線方法去分析電磁能隙結構，並結合去耦合電容研究其對抑制接地彈跳雜訊的影響。

In recent high-speed digital circuits with pico-second rising/falling edges, it is reasonable to consider the power/ground planes as a dynamic electromagnetic system. The simultaneous switching noise (SSN) or ground bounce noise (GBN), resulting from the transient currents which flow between power/ground planes during the state transitions of the logic gates, has become a critical factor to degrade the signal integrity (SI) and power integrity (PI) in PCB or package design. In order to accurately perform overall system-level power integrity simulation, extracting the SPICE-compatible models with the resonant effect being considered in the power/ground planes and incorporating the model into the conventional circuit simulator, such as SPICE, is essential.
In this thesis, a two-dimensional transmission line (2D-TL) model is proposed for constructing the SPICE-compatible model of the power/ground planes. Based on this model, the ground bounce noise for the BGA package mounted on a PCB can be efficiently evaluated. It is found that the behavior of GBN between the only package and package mounted on a PCB (hybrid structure) is obvious different. Then, we combine the SPICE-compatible model of the power/ground planes with decoupling capacitors to fast evaluate the behavior of GBN. It also has a good agreement between our model and the measured result.
Adding decoupling capacitors between the power and ground planes is a typical way to suppress the GBN. However, they are not effective at the frequency higher than GHz due to their inherent lead inductance. In recent, a new method for eliminating the GBN at higher frequency is proposed by electromagnetic bandgap (EBG) structure with high impedance surface (HIS). Finally, we utilize 2D-TL model to fast analyze the behavior of the EBG, and combine decoupling capacitors with EBG structure to research the suppression of the GBN.

目錄
圖表索引
第一章 序 1
1.1 研究目的與方法 1
1.2 論文大綱 3
第二章 接地彈跳雜訊 4
2.1 接地彈跳雜訊成因 4
2.2 接地彈跳雜訊現象與影響 6
2.3 印刷電路板的共振頻率點 7
2.4 印刷電路板的設計 9
2.4.1 印刷電路板上的輻射源 9
2.4.2 多層印刷電路板 11
2.4.3 接地面的完整性 12
2.5 常見抑制接地彈跳雜訊的對策 14
2.5.1 切割電源平面對接地彈跳雜訊的抑制效果 14
2.5.2 High impedance surface(HIS)對接地彈跳雜訊的抑制效果 18
2.5.3 去耦合電容對接地彈跳雜訊的抑制效果 19
第三章 數值模擬方法 21
3.1 簡介 21
3.2 二维傳輸線模型 22
3.2.1 基本單元與等效電路 22
3.2.2 Power/Ground Plane等效模型 23
3.3 模擬結果 24
3.3.1 電源裸版測試 24
3.3.2 接地彈跳雜訊共振效應 26
3.3.3 切換雜訊的時域模擬 30
第四章 封裝與PCB系統 33
4.1 電源系統架構之描述 33
4.2 封裝與PCB系統量測與結果 35
4.3 封裝與PCB系統之二维傳輸線模擬 38
4.3.1 封裝與PCB系統 38
4.3.2 封裝與PCB系統─加去耦合電容 40
第五章 去耦合電容對電源雜訊影響 45
5.1 電容在封裝與PCB系統之理想位置 45
5.2 去耦合電容寄生元件的影響 47
5.2.1 去耦合電容等效串聯電阻(ESR) 47
5.2.2 去耦合電容等效串聯電感(ESL) 48
5.3 電容數量和容值的影響 50
5.3.1 電容數量的影響 50
5.3.2 電容容值的選擇 51
5.4 板層厚度的影響 55
5.5 總結 59
第六章 以電磁能隙(EBG)結構抑制接地彈跳雜訊 60
6.1 電磁能隙簡介 60
6.2 以二維傳輸線模擬電磁能隙 61
6.3 結合去耦合電容與電磁能隙抑制電源雜訊 67
第七章 結論 71
參考文獻 72

[1] N. Na, M. Swaminathan, J. Libous, and D. O'Connor, “Modeling and simulation of core switching noise on a package and board,” Elec. Comp. and Tech. Conf., 2001, pp. 1095-1101.
[2] J. G. Yook, V. Chandramouli, L. P. B. Katehi, K. A. Sakallah, T. R. Arabi, and T. A. Schreyer, “Computation of switching noise in printed circuit boards,” IEEE Trans. Comp., Packag., and Manufact., vol. 20, Mar. 1997, pp. 64-75.
[3] G. T. Lei, R. W. Techentin, and B. K. Gilbert, “High-frequency characterization of power/ground-plane structures,” IEEE Trans. Microwave Theory Tech., vol. 47, May. 1999, pp. 562-569.
[4] N. Jain, J. Silvestro, Z. Cendes, and S. Potluri, “SI issues associated with high speed packages,” Elec. Packag. Tech. Conf., 1997, pp. 310 -312
[5] S. Van den Berghe, F. Olyslager, D. De Zutter, J. De Moerloose, and W. Temmerman, “Study of the ground bounce caused by power plane resonances,” IEEE Trans. Electromagn. Compat., vol. 40, May 1998, pp.111-119.
[6] J. N. Hwang and T. L. Wu, “Coupling of the ground bounce noise to the signal trace with via transition in partitioned power bus of PCB,” IEEE Int. Symp. Electromagn. Compat., 2002, pp. 733 -736.
[7] T. Tarvainen, “Studies on via coupling on multilayer printed circuit boards,” Dep. Of Elec. Engineer., Univer. of Oulu and Esju Oy, Oulu, Finland, 1999.
[8] J. Fang, J. Zhao, and J. Zhang, “Shorting via arrays for the elimination of package resonance to reduce power supply noise in multi-layered area-array IC packages,” IEEE Symp. IC/Packag. Desig. Integra., 1998, pp. 116 -119.
[9] Y. Xiaoning, M. Y. Koledintseva, L. Min, and J. L. Drewniak, “DC power-bus design using FDTD modeling with dispersive media and surface mount technology components,” IEEE Trans. Electromag. Compat., vol. 43, Nov 2001, pp. 579 -587.
[10] J. Chen, T. H. Hubing, T. P. Van Doren, and R. E. DuBroff, “Power bus isolation using power islands in printed circuit boards,” IEEE Trans. Electromag. Compat., vol. 44, May 2002, pp. 373 -380.
[11] C. Wei, F. Jun, R. Yong, S. Hao, J.L. Drewniak, and R.E.DuBroff, “DC power bus noise isolation with power-plane segmentation,” IEEE Trans. Electromag. Compat., vol. 45, pp. 436-443, May 2003.
[12] J. Chen, M. Xu, T. H.Hubing, J. L. Drewniak, T. P. Van Doren, and R. E. Dubroff, “Experimental evaluation of power bus decoupling on a 4-layer printed circuit board,” IEEE Int. Symp. Electromag. Compat., 2000, pp. 335-338.
[13] W. Cui, J. Fan, H. Shi, and J. L. Drewniak, “DC power bus noise isolation with power islands,” IEEE Int. Symp. Electromag. Compat., 2001, pp.899-903.
[14] H. Shi, J.Fan, J. L. Drewniak, T. H. Hubing, and T. P. van Doren, “Modeling multilayered PCB power-bus designs using MPIE based circuit extraction technique”, IEEE Int. Symp. Electromag. Compat., 1998, pp.652-655.
[15] J. Yun and T. H. Hubing, “On the interior resonance problem when applying a hybrid FEM/MoM approach to model printed circuit boards,” IEEE Trans. Electromag. Comp., vol. 44, May 2002, pp. 318 -323.
[16] T. L. Wu, Y. H. Lin, J. N. Hwang, and J. J. Lin, “The effect of test system
impedance on measurements of ground bounce in printed circuit boards,” IEEE Trans. Electromag. Compat. , vol. 43, Nov 2001, pp. 600 -607.
[17] T. Sudo, Y. Ko, S. Sakaguchi, T. Tokumaru, “Electromagnetic radiation and simultaneous switching noise in a CMOS device packaging,” Electronic Components and Technology Conference, , pp. 781-785, 21-24 May 2000.
[18] Y. H. Lin and T. L. Wu, “Investigation of signal quality and radiated emission of microstrip line on imperfect ground plane: FDTD analysis and measurement,” in Proc. IEEE Int. Symp. Electromagnetic Compatibility, Montreal, Canada, Aug. 2001, pp. 319-324.
[19] J. N. Hwang, T. L. Wu, “The bridging effect of the isolation moat on the EMI caused by ground bounce noise between power/ground planes of PCB,” Electromagnetic Compatibility, 2001. EMC. 2001 IEEE International Symposium on , Volume: 1, pp. 471-474 , 13-17 Aug. 2001.
[20] R. Abhari, and G. V. Eleftheriades, “Metallo-dielectric electromagnetic bandgap structures for suppression and isolation of the parallel-plate noise in high-speed circuits,” IEEE Trans. Microwave Theory & Tech., vol. 51, pp. 1629-1639, June 2003.
[21] T. Kamgaing, and O. M. Ramahi, “A novel power plane with integrated simultaneous switching noise mitigation capability using high impedance surface,” IEEE Microwave and Wireless Components Letters, vol. 13, pp. 21-23, January 2003.
[22] D. F. Sievenpiper, “High-impedance electromagnetic surfaces,”Ph.D. dissertation, Dept. Elect. Eng., Univ. California at Los Angeles, Los Angeles, CA, 1999.
[23] Keunmyung Lee and Alan Barber “Modeling and Analysis of Multichip Module Power Supply Planes,” IEEE Transactions on Components, Packaging Technology-Part B, VOL.18, NO.4, pp.628-639, November 1995.
[24] Joong-HO Kim, Madhavan Swaminathan and Youngsuk Suh, “Modeling of Power Distribution Networks for Mixed Signal Applications,” Electromagnetic Compatibility, 2001 International Symposium on, vol.2, pp.1117-1122, 2001
[25] M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley, 1998.
[26] N. Na, J. Choi, S. Chun, M. Swaminathan, and J. Srinivasan, “Modeling and transient simulation of planes in electronic packages,” IEEE Trans. Adv. Packag., vol. 23, pp.340–352, Aug. 2000.
[27] S.T. Chen, C.W. Tsai, S.M. Wu, C.P. Hung, T.L. Wu, “Chip-level model of switching noise coupling on integrated system combining package and printed circuit board,” EMC Europe 2004,, Vol. 1, pp. 420-424, Eindhoven, Netherland, Sept. 2004
[28] Jun Fan, Drewniak, J.L., Knighten, J.L., Smith, N.W., Orlandi, A., Van Doren, T.P., Hubing, T.H., DuBroff, R.E., “Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs”, IEEE Trans. Electromag. Compat., vol. 43, Nov 2001, pp. 588 –599.
[29] Gisin, F.; Pantic-Tanner, Z., “Edge emissions from a PC board structure, ” in Proc. of IEEE Int. Symp. on EMC, 2001, pp. 1333-1334.
[30] T. L. Wu, Y. H. Lin and S. T. Chen, “A Novel Power Planes With Low Radiation and Broadband Suppression of Ground Bounce Noise Using Photonic Bandgap Structures,” IEEE Microwave and Wireless Components Letters, vol. 14, pp. 337-339, July 2004.
[31] R. Coccioli, F. R. Yang, K. P. Ma and T. Itoh, “Aperture-coupled patch antenna on UC-PBG substrate,” IEEE Trans. Microwave Theory & Tech., vol. 47, pp. 2123-2130, Nov. 1999.
[32] N. Shino and Z. Popovic´, “Radiation from ground-plane photonic bandgap microstrip waveguide,” IEEE MTT-S Int. Microwave Symp. Dig., June 2002, pp. 1079–1082.