構裝體中各材料熱膨脹係數差異引致的熱應變，及系統操作溫度反覆變化所致的疲勞效應，為覆晶接合的焊錫凸塊破壞最主要的原因。本研究目的即在於瞭解當無鉛覆晶構裝受溫度循環測試時，各元件幾何參數變異對其熱疲勞壽命的影響。首先，藉由有限元素分析模擬無鉛覆晶構裝受熱負載後的響應情形，使用無鉛凸塊受溫度循環後所累積的等效潛變應變和等效潛變應變能來預估其熱疲勞壽命。其次，應用田口法求得無鉛覆晶構裝結構於熱循環測試條件下最佳的幾何參數設計，並應用變異數分析評估影響結構可靠度最具影響力的幾何因子。本研究結果可用以作為無鉛覆晶構裝可靠度設計的參考。

Thermal fatigue failure, due to the fracture of solder bumps which was cased by the coefficient of thermal expansion mismatch deformation, is frequently encountered in flip-chip package. Therefore, this thesis attempts to study the effects of geometric parameters variation on lead-free flip-chip package under temperature cycling test. First, we used the finite element method to simulate the thermal loading response of lead-free flip-chip. The accumulated equivalent creep strain and accumulated creep strain energy density of the lead-free solder bumps were calculated, and were used to predict the thermal fatigue life of lead-free flip-chip package. The Taguchi method is applied to obtain the optimal design parameters in order to enhance reliability of the lead-free flip-chip under temperature cycling loading. The analysis of variance (ANOVA) is also used for estimating the influence of the factors quantitatively. The obtained results can be adopted as references for the lead-free flip-chip package design.

Contents i
List of Tables iv
List of Figures v
摘要 vii
Abstract viii

Chapter1 Introduction 1
1.1 Background of IC Package 1
1.2 Lead-Free Solder Material 3
1.3 Literatures Rewiew 5
1.3.1 Analysis in Solder Bump Configuration 6
1.3.2 Underfill Material Analysis in Package 8
1.3.3 Different Eutectic Solder Material Types 9
1.3.4 Thermal Fatigue Analysis of Lead-Free Solder 10
1.3.5 The Thermal Loading Simulations in FEM 11
1.4 Research Objectives 12
1.5 Content Frame 13

Chapter2 Fundamental Theories 16
2.1 Physical Phenomenon of Fatigue 16
2.2 Creep Model of Solder Bump 17
2.3 Fatigue Life Prediction Models 19
2.4 Taguchi Method and Analysis of Variance 20
2.4.1 Taguchi Method 20
2.4.2 Analysis of Variance 22

Chapter3 Numerical Simulation 27
3.1 Basic Assumptions 28
3.2 Geometrical Model of the Flip-Chip Package 29
3.3 The Material Properties 30
3.4 FEM Mesh and Boundary Condition 31
3.5 The Thermal Loading 31
3.6 Accuracy of Mesh 33
3.7 Analysis Procedure 33

Chapter4 Results and Discussions 43
4.1 Validation of Finite Element Model 43
4.2 Response of Solder Bumps 44
4.2.1 Equivalent Stress and Equivalent Creep Strain 44
4.2.2 Accumulated Creep Strain and Creep Strain Energy Density 45
4.2.3 Creep Hysteresis Loops 47
4.3 Comparison of SnAgCu and SnPb Solder Bumps 47
4.4 Effects of Temperature Cycle Profile 48
4.4.1 Effect of Temperature Range on the Solder Fatigue Life 48
4.4.2 Effect of Dwell Time on the Solder Fatigue Life 49
4.4.3 Effect of Ramp Rate on the Solder Fatigue Life 49
4.5 Taguchi Method Design 49
4.5.1 Selection of Quality Factor 50
4.5.2 Control Factors and Levels 50
4.5.3 Main Experiment Simulation 52
4.5.4 Confirmation Simulation 53

Chapter5 Conclusions 73
5.1 Conclusions 73
5.2 The Future Works 74

Reference 75

1. 高全德，無鉛銲錫---BGA篇，工研院ITIS，2001。
2. 高全德，構裝用無鉛銲錫材料發展趨勢，工研院ITIS，2001。
3. Q. Yu, M. Shiratori, and Y. Ohshima, “A Study of the Effects of BGA Solder Geometry on Fatigue Life and Reliability Assessment,” Inter Society Conference on Thermal Phenomena, pp. 229-235, 1998.
4. T. H. Ho, J.Y. Lee, R. S. Lee, and A. W. Lin, “Linear Finite Element Stress Simulation of Solder Joints on 225 I/O Plastic BGA Package Under Thermal Cycling,” Electronic Components and Technology Conference, pp. 930-936, 1995.
5. H. Sakal, N. Yamaoka, K. Ujile, and M. Motegl, “Shape Prediction and Residual Stress Evaluation of BGA and Flip Chip Solder Joints,” Inter Society Conference on Thermal Phenomena, pp. 181-186, 2000.
6. B. Su, S. Hareb, Y. C. Lee, M. J. Lii, and M.E. Thurston, “Solder Joint Reliability Modeling for a 540-I/O Plastic Ball-Grid-Array Assembly,” Proceedings of the International Conference on Multichip Modules and High Density Packaging, pp. 422-428, 1998.
7. C. T. Peng, H. C. Cheng, and K. N. Chiang, “Reliability Analysis and Design for the Fine-Pitch Flip Chip BGA Packaging,” Transactions on Components and Packaging Technologies, Vol. 27, No. 4, pp. 684-693, 2004.
8. Z. Qian, M. Lu, R. Wei, and S. Liu, “Fatigue Life Prediction of Flip-Chips in Terms of Nonlinear Behaviors of Solder and Underfill,” Electronic Components and Technology Conference, pp. 141-148, 1999.
9. J. H. Lau and S. W. R. Lee, “Effects of Build-Up Circuit Board Thickness on The Solder Joint Reliability of a Wafer level Chip Scale Package (WLCSP),” Transactions on Components and Packaging Technologies, Vol. 25, No. 1, pp.3-14, 2002.
10. L. Mercado, V. Sarihan, Y. Guo, and A. Mawer, “Impact of Solder Pad Size on Solder Joint Reliability in Flip Chip PBGA Packages,” Transactions on Advanced Packaging, Vol. 23, No. 3, pp. 415-420, 2000.
11. T. J. Goh, “Parametric Finite Element Analysis of Solder Joint Reliability of Flip Chip On Board,” Electronics Packaging Technology Conference, pp. 57-62, 1998.
12. W. R. Jong, S. C. Chen, H. C. Tsai, C. C. Chiu, and H. T. Chang, “The Geometrical Effects of Bumps on the Fatigue Life of Flip-Chip Packages by Taguchi Method,” Journal of Reinforced Plastics and Composites, Vol. 25, No. 1, pp. 99-114, 2006.
13. T. Burnettel, Z. Johnson, T. Koschmieder, and W. Oyler, “Underfilled BGAs for Ceramic BGA Packages and Board-Level Reliability,” Electronic Components and Technology Conference, pp. 1221-1226, 2000.
14. J. Pyland, R. V. Pucha, and S. K. Sitaraman, “Thermalmechanical Reliability of Underfilled BGA Packages,” Transactions on Electronics Packaging Manufacturing, Vol. 25, No. 2, pp. 100-106, 2002.
15. D. G. Yang, G. Q. Zhang, L. J. Ernst, C. V. Hof, J. F. J. Caers, H. J. L. Bressers, and J. H. J. Janssen, “Investigation on Flip Chip Solder Joint Fatigue with Cure-Dependent Underfill Properties,” Transactions on Components and Packaging Technologies, Vol. 26, No. 2, pp. 388-398, 2003.
16. Z. N. Cheng, L. Chen, G. Z. Wang, X. M. Xie, and Q. Zhang, “The Effects of Underfill and Its Material Models on Thermomechanical Behaviors of Flip Chip Package,” Int’l Symp on Electronic Materials and Packaging, pp. 232-239, 2000.
17. K. N. Chiang, Z. N. Liu, and C. T. Peng, “Parametric Reliability Analysis of No-Underfill Flip Chip Package,” Transactions on Components and Packaging Technologies, Vol. 24, No. 4, pp. 635-640, 2001.
18. J. Y. Deletage, A. Fenech, L. Bechou, Y. Ousten, Y. Danto, M. Salagoity, C. Faure, and S. Rao, “Thermomechanical Behavior of Ceramic Ball Grid Array Based on Experiments and FEM Simulations,” International Electronics Manufacturing Technology Symposium, pp. 91-98, 1996.
19. J. Wang, W. Ren, D. Zou, Z. Qian, and S. Liu, “Processing Mechanics for Flip-Chip Assemblies,” Computers and Structures, Vol. 71, pp. 457-468, 1999.
20. A. Yeo, C. Lee, and J. H. L. Pang, “Flip Chip Solder Joint Reliability Analysis Using Viscoplastic and Elastic-Plastic-Creep Constitutive Models,” Transactions on Components and Packaging Technologies, Vol. 29, No. 2, pp. 355-363, 2006.
21. J. H. L. Pang, P. T. H. Low and B. S. Xiong, “Lead-Free 95.5Sn-3.8Ag-07.Cu Solder Joint Reliability Analysis for Micro-BGA Assembly,” Inter Society Conference on Thermal Phenomena, pp. 131-136, 2004.
22. M. Gonzalez, B. Vandevelde and E. Byene, “Thermo-Mechanical Analysis of a Chip Scale Package (CSP) Using Lead Free and Lead Containing Solder Materials,” European Microelectronics and Packaging Symposium, pp. 247-252, 2004.
23. J. H. L. Pang, A. Yeo, T. H. Low and F. X. Che, “Lead-Free 96.5Sn-3.5Ag Flip Chip Solder Reliability Analysis,” Inter Society Conference on Thermal Phenomena, pp. 160-164, 2004.
24. M. Roellig, R. Dudek, S. Wiese, B. Boehme, B. Wunderle, K. J. Wolter and B. Michel, “Fatigue Analysis of Miniaturized Lead-Free Solder Contacts Based on a Novel Test Concept,” Microelectronics Relaibility, Vol. 47, pp. 187-195, 2007.
25. B. Vandevelde, M. Gonzalez, P. Limaye, P. Ratchev and E. Beyne, “Thermal Cycling Reliability of SnAgCu and SnPb Solder Joints A Comparison for Several IC-Packages,” Microelectronics Relaibility, Vol. 47, pp. 259-265, 2007.
26. X. Li and Z. Wang, “Thermo-Fatigue Life Evaluation of SnAgCu Solder Joints in Flip Chip Assemblies,” Journal of Materials Processing Technology, Vol. 183, pp. 6-12, 2007.
27. A. Syed, “Accumulated Creep Strain and Energy Density Based Thermal Fatigue Life Prediction Models for SnAgCu Solder Joints,” Electronic Components and Technology Conference, pp. 737–746, 2004.
28. I. Shohji, H. Mori, and Y. Orii, “Solder Joint Reliability Evaluation of Chip Scale Package Using a Modified Coffin-Manson Equation,” Microelectronics Reliability, Vol. 44, pp. 269-274, 2004.
29. T. Dishongh, C. Basaran, A. N. Cartwright, Y. Zhao, and H. Liu, “Impact of Temperature Cycle Profile on Fatigue Life of Solder Joints,” Transactions on Advanced Packaging, Vol. 25, No. 3, pp. 433-438, 2002.
30. J. Lau and W. Dauksher, “Effects of Ramp-Time on the Thermal-Fatigue Life of SnAgCu Lead-Free Solder Joints,” Electronic Components and Technology Conference, pp. 1292-1298, 2005.
31. X. Fan, G. Raiser and V. S. Vasudevan, “Effects of Dwell Time and Ramp Rate on Lead-Free Solder Joints in FCBGA Packages,” Electronic Components and Technology Conference, pp. 901-906, 2005.
32. W. W. Lee, L. T. Nguyen and Selvaduray, “Solder Joint Fatigue Models: Review and Applicability to Chip Scale Packages,” Microelectronics Reliability, Vol. 40, pp. 231-244, 2004.
33. R. K. Roy, “A Primer on the Taguchi Method,” Van Nostrand Reinhold, New York, 1990.
34. R.A. Fisher, “Statistical Methods for Research Workers,” Oliver & Boyd, Edinburgh, 1925.