表面保護(Surface Passivation)與抗反射效果(Anti-Reflection)為影響背面接觸光伏元件轉換效率的主要因素之一，因此減少反射光之損失以提升其捕捉光的能力以及降低載子複合所造成之損失可有效提升光伏元件的轉換效率。為了達到上述目的以實現高效率背面接觸光伏元件於標準塊材金氧半製程，本論文首先利用機械研磨的方式薄化元件基板厚度，經研磨後使晶片總體厚度降低以除去金氧半製程過程於矽基板中大量產生的氧空缺，同時並減少基板電阻以提升光電流捕捉效率。經過此一研磨過程後，元件之轉換效率均有明顯的提升(0.35-m CMOS PV:4.31%→12.84%、0.18-m CMOS PV:2.47%→14.2%、0.18-m CMOS DNW PV:6.81%→16.65%)。緊接著我們進行超臨界二氧化碳流體製程以鈍化晶片背面矽基板達到表面保護的效果。藉由超臨界流體有效地氧化基板表面，降低表面載子複合提升少數載子的生命週期，以提升短路電流。相較於其他方法，像是熱氧化法或藉由電漿輔助物理氣相沉積於元件表面沉積上氮化矽屬於高溫製程。超臨界流體製程屬於低溫製程(120°C)，可避免光伏元件因高溫造成結構破壞。隨後將超臨界流體製程與金屬輔助蝕刻製程整合，先於基板蝕刻出隨機排列的奈米線結構以降低表面反射率，經蝕刻後表面反射率可從初始之30~40%降低至2~4%左右，同時由於接觸面積的上升也可增加超臨界流體製程於表面的氧化效果，表面的氧含量上升12.3%，而一般拋光基板於超臨界流體製程後氧含量僅增加3.6%。在經過這兩個製程後，光伏元件之轉換效率可從16.65%增加至21.22%。

Surface passivation and antireflection strongly affect the conversion efficiency of back-contact CMOS photovoltaic devices. Enhanced device performance is obtained by reducing the surface reflection and the minority carrier recombination. In order to achieve efficient back-contact CMOS photovoltaic device in standard bulk CMOS process, in this work we thin down the device substrate by mechanical grinding and lapping process in order to remove low-lifetime bulk substrate and increase the photocurrent collection efficiency. Thinned photovoltaic devices show an increase in conversion efficiency from originally 2~6% to 12~16% depending on the CMOS process. Supercritical carbon dioxide fluid process is then conducted for surface passivation of CMOS photovoltaic devices in order to reduce the surface recombination and thus increase the short-circuit current. Compared to other passivation techniques such as thermal oxidation or PECVD oxide deposition that requires high-temperature atmosphere, supercritical CO2 fluid is a low-temperature process that is much suitable to serve as the back-end process for CMOS photovoltaic devices. Afterward, a metal-assisted chemical etching process is then conducted to produce random silicon nanowire array to reduce the surface reflectivity from originally 30~40% down to only 2~4%. Enlarge surface area in silicon nanowire array also leads to a higher oxygen content after supercritical CO2 fluid treatment, as compared to planar surface. All efforts lead to an ultimate efficiency of 21.22% in silicon nanowire decorated back-contact CMOS photovoltaic devices.

中文審定書 i
英文審定書 ii
致謝 iii
摘要 iv
Abstract v
內容目錄 vi
圖目錄 ix
表目錄 xiii
第一章 緒論 1
1.1 前言 1
1.2 太陽能電池原理 1
1.3 太陽能電池之電性參數介紹 3
1.3.1 短路電流(Short Circuit Current, ISC) 4
1.3.2 開路電壓(Open Circuit Voltage, VOC) 5
1.3.3 填充因子(Fill Factor, FF) 5
1.3.4 轉換效率(Conversion Efficiency, η) 6
1.4 影響轉換效率之因素 6
1.5 奈米結構成長之技術原理與應用 9
1.6 超臨界流體之技術與應用 13
1.7研究動機 16
1.8 論文架構 19
第二章 儀器與製程介紹 20
2.1 量測儀器及量測架構介紹 20
2.1.1 IPCE量測系統 20
2.1.2 拉曼光譜儀(Raman Spectroscopy) 22
2.1.3 X光光電子能譜儀(XPS) 23
2.1.4 掃描式電子顯微鏡(SEM) 25
2.1.5 量測系統架構 27
2.2標準CMOS製程架構設計之光伏元件介紹 29
2.2.1製程介紹與限制 29
2.2.2下線晶片介紹 31
2.3 元件基板研磨製程 35
2.4 矽奈米線之成長 37
2.4.1 元件前處理流程 37
2.4.2 催化劑金薄膜沉積 37
2.4.3 矽奈米線蝕刻 38
2.5 超臨界流體系統 40
第三章 量測結果與討論 42
3.1 光伏元件研磨量測結果及討論 42
3.2 超臨界二氧化碳量測結果分析 49
3.2.1 元件表面分析 49
3.2.2 太陽能電池量測結果 51
3.3 表面矽奈米線量測結果分析 54
3.3.1 表面奈米線結構分析 54
3.3.2 太陽能電池量測結果 56
3.4 表面矽奈米線暨超臨界二氧化碳量測結果分析 58
3.4.1 元件表面分析 58
3.4.2 太陽能電池量測結果 61
第四章 結論 63
4.1 成果與討論 63
4.2 未來改善方向 64
參考文獻 66
附錄 73

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