本研究使用標準互補式金氧半CMOS製程中高解析度離子佈植與多層金屬連接層的特性，設計積體化背部接觸光伏元件架構，所有設計皆遵循標準CMOS製程的佈局法則與製程步驟，並通過多項物理驗證，故此光伏元件可直接與其他積體電路整合，以實現自我供電微系統。考量標準CMOS製程使用的矽晶圓中含有高濃度的氧缺陷，只有距離表面約10~20 µm以內為具有高載子生命週期之無缺陷區域，加上其矽晶片具有高電阻與厚度較厚的特性，嚴重影響背面接觸光伏元件的光電流擷取效率以及最終光電轉換效率。原始625 µm厚的光伏元件在1mW/mm2 980 nm近紅外光的照射下，其轉換效率僅為1~2 %，並僅能產生0.022 mW/mm2能量。為了提升整體元件的光電流轉換效率，我們利用自行後製程研磨技術薄化基板至約75 µm，成功提升轉換效率達10 %以上，並可產生至少0.13 mW/mm2以上的能量。在植入式生醫晶片遠端供電的應用上，此光伏元件在生物組織的覆蓋下仍可產生159 µW的能量。為了要更進一步的提升光伏元件的效能，我們在原始的架構中利用CMOS製程上具有多層金屬層的特性將第二層以上的金屬設計成反射鏡架構來讓長波段的光源能反射回基板做二次光電轉換，同時我們藉由改變重摻雜區上的via金屬層之間的距離來探討金屬層的反射特性，最終得到週期在7 m以上時的反射率可達70 %以上。藉由P-N接面的最大化以及背面金屬反射鏡的最佳化，我們更成功實現效率達20 %之CMOS背部接觸光伏元件。在抗反射結構的實現上，我們使用四甲基氢氧化铵(TMAH)將矽基板表面做粗糙化，使矽基板表面的反射率從原本30-40 %下降到2 %以下。同時我們將金字塔抗反射結構做在同製程、同厚度和同設計的光伏元件上，成功地提升其轉換效率將近9 %。

In this thesis, an interdigitated back-contact photovoltaic device is realized by high-resolution doping and multi-layer interconnections provided by standard bulk CMOS processes. Since the device designs strictly follow the standard CMOS process procedures, this photovoltaic device can be directly integrated with other microelectronic circuits to realize a self-powered system. In general, the starting silicon wafer for CMOS usually has a high-lifetime denuded zone within 10-20 microns from the surface and a low-lifetime bulk with high defect densities. Such a thick and high-resistivity silicon wafer having a non-uniform bulk material lifetime is detrimental to photovoltaic device performance since the entire volume of the wafer is involved in cell operation. In order to boost the photocurrent collection efficiency, we develop an in-house post grinding process to thin down the substrate in order to increase the conversion efficiency to >10 % and a generated electrical power of 0.13 mW/mm2. With the help of maximized interdigitated junction design and metal reflective mirrors, the proposed photovoltaic device is able to provide a conversion efficiency of up to 20 %. For surface antireflection technique, the device is rinsed in a TMAH solution to create pyramid structures atop planar silicon surface, thus leading to reduced surface reflectivity from originally 30~40 % to only 2 % and an improved device efficiency by 9 %.

目錄
論文審定書 i
致謝 ii
中文摘要 iii
英文摘要 iv
第一章序論 1
1-1 前言 1
1-2 研究動機 2
1-3 文獻回顧 6
1-4 論文架構 11
第二章太陽能電池原理及模擬 12
2-1 太陽能電池原理 12
2-2 等效電路簡介 13
2-3 太陽能電池參數介紹 14
第三章下線晶片與實驗製程介紹 21
3-1 製程分析與介紹 21
3-2 下線晶片介紹 23
3-3 晶片後製程介紹 33
3-4 抗反射結構製作 36
第四章量測結果分析與比較 44
4-1 量測系統架構 44
4-2 元件數據分析 46
第五章結論 54
5-1 成果與討論 54
5-2 未來研究方向 55
參考文獻 59
附錄 62

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