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博碩士論文 etd-0629110-123305 詳細資訊
Title page for etd-0629110-123305
論文名稱
Title
適用於低ISM頻帶之自動取樣ASK解調變器與同步自動校正數位類比轉換器
Self-sampled All-MOS ASK Demodulator & Synchronous DAC with Self-calibration for Bio-medical Applications
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
56
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2010-06-22
繳交日期
Date of Submission
2010-06-29
關鍵字
Keywords
數位類比轉換器、ISM頻帶、自動取樣、ASK解調變器、自動校正
self-calibration, ISM band, self-sampled, ASK demodulator, DAC
統計
Statistics
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中文摘要
本論文提出兩個新的電路設計, 一為適用於低ISM 頻帶之自動取樣ASK (Amplitude shift keying) 解調變器, 以及另一為同步自動校正數位類比轉換器。
第一主題提出的ASK 解調變器架構採用無被動元件的設計, 以減少面積的消耗, 這對於無線生物醫學電子的應用是一個很大的貢獻。因為低面積消耗和低功率消耗, 本電路設計可以整合在攜帶式的生物醫學裝置, 並且適用於低的ISM 頻帶。為了驗證本電路架構, 我們使用了TSMC
0.35 μm 標準CMOS 製程來實現並量測效能。
第二主題提出一個可同步自動校正的數位類比轉換器, 主要是利用自動校正的電路來克服因為單位電容太小所導致的輸出電壓誤差變大。在校正之前INL 的結果大於1.7 LSB, 在校正之後INL 的結果小於0.5 LSB。我們也使用TSMC 0.18μm 標準CMOS 製程來實現並量測效能。
Abstract
This thesis includes two topics, which are a Self-sampled ALL-MOS ASK Demodulator and a Synchronous DAC with Self-calibration.
An all-MOS ASK demodulator with a wide bandwidth for lower ISM band applications is presented in the first half of this thesis. The chip area is reduced without using any passive element. It is very compact to be integrated in an SOC (system-on-chip) for wireless biomedical applications, particularly in biomedical implants. Because of low area cost and low power consumption, the proposed design is also easily to be integrated in other mobile medical devices. The self-sampled loop with a MOS equivalent capacitor compensation mechanism enlarges the bandwidth, which is more than enough to be adopted in any application using lower ISM bands. To demonstrate this technique, an ASK demodulator prototype is implemented and measured using a TSMC 0.35 μm standard CMOS process.
The second topic reveals a synchronous DAC with self-calibration. The main idea is to use a calibration circuit to overcome large error of output voltage caused by the variation of the unit capacitor. When DAC is not calibrated, INL is larger than 1.7 LSB. After calibrated, INL is improved to be smaller than 0.5 LSB. To demonstrate this technique, a DAC prototype is implemented and measured using a TSMC 0.18 μm standard CMOS process.
目次 Table of Contents
Contents
摘要i
Abstract ii
Contents iii
List of Figures vi
List of Tables viii
1 INTRODUCTION 1
1.1 Introduction to SCS . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . 4
1.2.1 All-MOS ASK demodulator . . . . . 4
1.2.2 DAC with calibration design . . . . . 4
1.3 Literature review . . . . . . . . . . . . . . . 5
1.3.1 ASK demodulator design . . . . . . . 5
1.3.2 DAC with calibration design . . . . . 6
1.4 thesis overview . . . . . . . . . . . . . . . . 7
2 SELF-SAMPLED ALL-MOS ASK DEMOD-
ULATOR 8
2.1 Introduction to ASK demodulator . . . . . . 8
2.2 ASK demodulator design . . . . . . . . . . . 9
2.2.1 Rectifier and envelope detector design 9
2.2.2 Digital shaper design . . . . . . . . . 11
2.2.3 Noise analysis . . . . . . . . . . . . . 12
2.2.4 Self-sampled Loop . . . . . . . . . . 13
2.2.5 Load Driver . . . . . . . . . . . . . . 15
2.3 Simulation . . . . . . . . . . . . . . . . . . . 15
2.3.1 Simulation of ASK demodulator . . . 15
2.3.2 Die photo and layout . . . . . . . . . 17
2.4 Measurement . . . . . . . . . . . . . . . . . 17
2.5 Summary . . . . . . . . . . . . . . . . . . . 19
3 SYNCHRONOUS DACWITH SELF-CALIBRATION 21
3.1 Architecture of the proposed DAC . . . . . . 21
3.2 Design of Sub-system Circuits . . . . . . . . 22
3.2.1 Main DAC . . . . . . . . . . . . . . . 24
3.2.2 OPA . . . . . . . . . . . . . . . . . . 25
3.2.3 Current DAC . . . . . . . . . . . . . 27
3.2.4 Control circuit . . . . . . . . . . . . 27
3.3 Simulation . . . . . . . . . . . . . . . . . . . 29
3.3.1 INL . . . . . . . . . . . . . . . . . . 31
3.3.2 DNL . . . . . . . . . . . . . . . . . . 32
3.3.3 Performance comparison . . . . . . . 32
3.3.4 Layout view . . . . . . . . . . . . . . 33
3.4 Measurement . . . . . . . . . . . . . . . . . 35
3.5 Summary . . . . . . . . . . . . . . . . . . . 37
4 CONCLUSION & FUTURE WORKS 38
REFERENCES 39
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