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博碩士論文 etd-0629112-092948 詳細資訊
Title page for etd-0629112-092948
論文名稱
Title
矽鍺氧化物薄膜在非揮發性記憶體應用之研究
The research of Silicon-Germanium-Oxide thin film in nonvolatile memory application
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
57
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2012-06-21
繳交日期
Date of Submission
2012-06-29
關鍵字
Keywords
矽鍺氧化物、非揮發性記憶體、電阻式記憶體、參雜氮、穩定性
stability, non-volatile memory, Si-Ge-O, nitrogen doping, RRAM
統計
Statistics
本論文已被瀏覽 5765 次,被下載 2806
The thesis/dissertation has been browsed 5765 times, has been downloaded 2806 times.
中文摘要
非揮發性記憶體(NVM)在目前所追求的操作特性為高密度記憶單元、低功率損耗、
快速讀寫操作、以及良好的可靠度(Reliability)。傳統浮動閘極(floating gate)記憶
體在操作過程中如果穿隧氧化層產生漏電路徑會造成所有儲存電荷流失到矽基
板,所以在資料保存時間(Retention)和耐操度(Endurance)的考量下,穿隧氧化層
的厚度將會有個物理上的極限存在,因此在尺寸的微縮上也有極限的存在。在次
世代的許多新型非揮發性記憶體中,電阻式記憶體被提出為一種選擇,由於電阻
式記憶體有幾個主要的優點:(1)結構簡單因此製程容易,成本降低;(2)在製程
微縮上所受限制較少;(3)具有同一位元的多筆資料存儲特性;(4)操作速度快,
可達10 奈秒;(5)重複寫入次數可到100 萬次以上。因此具有相當的機會成為下
一世代主流的揮發型記憶體元件。
實驗中,利用一個簡單、低溫的製程方法用來形成矽鍺氧化物(Si-Ge-O)電阻
式記憶體和與在電極/矽鍺氧化物介面上參雜氮原子的矽鍺氧化物(Si-Ge-O)電阻
式記憶體。室溫下,分別在氬氣和氧氣(Ar/O2)及氬氣和氨氣(Ar/NH3) 的環境中
濺鍍(sputtering)混合鈀材SiGe 形成矽鍺氧(Si-Ge-O)電阻式記憶體,及矽鍺氧
(Si-Ge-O)/矽鍺氧氮(Si-Ge-O-N)電阻式記憶體。利用氮的添加在於電極/矽鍺氧化
物介面上,進而改善寫入電壓的不穩定性與重覆操作的次數。另外矽,鍺皆為目
前光電產業常被使用的半導體材料,也是材料特性被廣泛研究的半導體材料,運
用此兩種材料作為基礎,來研究電阻式記憶體的電阻切換特性,進而改善
Retention 時間及切換電阻狀態時寫入電壓的穩定性。
Abstract
The operating characteristics of non-volatile memory for modern
requirement are high-density , low power consumption, fast read and
write speed, and good reliability.
The floating gate memory generated leakage path in the tunnel oxide
during the trend of scaling down, which will result in the loss of all stored
charge to the silicon substrate.
As the data retention time and endurance are taken into consideration,
the thickness of tunnel oxide exist a physical limit, owing to the demand
of high-density capacities.
RRAM is offered as an option in the next generation non-volatile
memories, due to the following advantages:
(1) simple structure and easy to process, and low cost ; (2) less
restrictive in the scaling-down process; (3) with the multi-bit data storage
features; (4) high speed operation; (5) Repeat write and read is more than
one million.
In the thesis, we use a simple and low-temperature process to form the
silicon germanium oxide (Si-Ge-O) RRAM and silicon germanium oxide
RRAM with nitrogen doping between the electrode and
silicon-germanium oxide interface.
By sputtering at argon and oxygen (Ar/O2), and sputtering at argon and
ammonia (Ar/NH3) with silicon-germanium target to form silicon
germanium oxide RRAM and silicon germanium oxide (Si-Ge-O)/silicon
germanium oxnitride (Si-Ge-O-N) RRAM. By informing a SiGeON layer
between the interface of electrode and silicon-germanium oxide improve
the stability of write voltage and endurance reliability.
In addition, both silicon and germanium are useful as materials in the
optoelectronics industry and extensively studied in material science.
Based on the two materials, the smiting characterizations of RRAM
will be improved in the read-write stability and operation reliability.
目次 Table of Contents
論文審定書------------------------------------------------------i
致謝-------------------------------------------------------------ii
中文摘要-----------------------------------------------------iiii
英文摘要-------------------------------------------------------iv
目錄--------------------------------------------------------------v
圖目錄------------------------------------------------------viiii
表目錄----------------------------------------------------------xi
第一章 緒論
1-1. 前言------------------------------------------------------1
1-2. 研究目的與動機--------------------------------------------5
第二章 文獻回顧與理論基礎
2-1.電阻式記憶體材料--------------------------------------------7
2-2.電阻轉換特性與機制介紹--------------------------------------8
2-2-1. 電阻絲理論-------------------------------------------9
2-2-2. 界面操作--------------------------------------------11
2-2-3. 氧化還原反應機制------------------------------------12
2-2-3-1 氧化還原反應過程-------------------------------13
2-3. 介電質導電機制--------------------------------------------15
2-3-1. 穿隧(Tunneling)-------------------------------------15
2-3-2. 蕭特基發射(Schottky emission)-----------------------15
2-3-3. 普爾-夫倫克爾發射(Poole-Frenkel emission)-----------16
2-3-4. 歐姆傳導(Ohmic conduction)--------------------------16
2-3-5. 空間電荷限制電流(space-charge-limited current)------17
第三章 實驗方法與步驟
3-1.實驗流程---------------------------------------------------18
3-2.樣品基材製備-----------------------------------------------18
3-3.實驗試片之製備---------------------------------------------19
3-3-1. 氮化鈦/矽鍺氧化物/鉑(TiN/SiGeO/Pt)電阻式記憶體試片製作
----------------------------------------------------19
3-3-2.氮化鈦/矽鍺氧氮化物/矽鍺氧化物/鉑(TiN/ SiGeON/SiGeO/Pt)
的電阻式記憶體試片製作-------------------------------19
3-4.電性量測分析法---------------------------------------------22
3-4-1. 量測氮化鈦/矽鍺氧化物/鉑(TiN/SiGeO/Pt)的電阻式記憶體
----------------------------------------------------22
3-4-2.量測氮化鈦/矽鍺氧氮化物/矽鍺氧化物/鉑
(TiN/SiGeON/SiGeO/Pt)電阻式記憶體--------------------24
第四章 實驗結果與討論
4-1.基本電性探討-----------------------------------------------25
4-1-1. 氮化鈦/矽鍺氧化物/鉑(TiN/SiGeO/Pt)的電阻式記憶體電性
量測與探討------------------------------------------------25
4-1-2. 氮化鈦/矽鍺氧氮化物/矽鍺氧化物/鉑
(TiN/ /SiGeON/SiGeO/Pt)電阻式記憶體電性量測與探討---------26
4-1-3. 試片比較分析與討論----------------------------------26
4-2. 阻態轉換特性分析------------------------------------------38
4-2-1. Pulse-IV 量測----------------------------------------42
4-2-1-1. Pulse-IV 實驗結果與討論-------------------------44
第五章 結論----------------------------------------------------47
參考文獻--------------------------------------------------------49
圖目錄
圖1-1-1 磁阻式記憶體記憶原理示意圖---------------------------------3
圖1-1-2 相變化記憶體操作原理示意圖---------------------------------3
圖1-1-3 鐵電記憶體操作原理示意圖-----------------------------------4
圖1-1-4 電阻式記憶體阻態切換IV電性圖-------------------------------4
圖2-2-1 (a)單極操作電流電壓特性圖(b)雙極操作電流電壓特性圖----------8
圖2-2-2 電阻絲示意圖------------------------------------------------9
圖2-3-3 利用導電式原子力顯微鏡觀察TiO2 絕緣層之低電阻態與高電阻態--10
圖2-2-4 電阻絲內部差排對溫度變化模擬圖-----------------------------10
圖2-2-5 電阻絲在電阻式記憶體內操作示意圖---------------------------10
圖2-2-6 界面操作控制機制示意圖--------------------------------11
圖2-2-7 固態電解質電化學反應示意圖---------------------------------12
圖2-2-8 界面上進行銅參雜的固態電解質電阻式記憶體,電流電壓特性圖-------------------------------------------------12
圖2-2-9 電極過程的反應途徑---------------------------------14
圖3-2-1 基板的側面剖面示意圖---------------------------------------18
圖3-3-1 氮化鈦/矽鍺氧化物/鉑(TiN/SiGeO/Pt)電阻式記憶體試片製作流程示意圖------------------------------------------------------20
圖3-3-2 氮化鈦/矽鍺氧氮化物/矽鍺氧化物/鉑(TiN/ SiGeON/SiGeO/Pt)的電阻 式記憶體試片製作流程示意圖---------------------------------21
圖 4-1-1 氮化鈦/矽鍺氧化物/鉑(TiN/SiGeO/Pt)的電阻式記憶Forming-process與IV 電性圖------------------------------------------------28
圖4-1-2 氮化鈦/矽鍺氧化物/鉑(TiN/SiGeO/Pt)的電阻式記憶體retention 圖
-------------------------------------------------------------------28
圖4-1-3 氮化鈦/矽鍺氧化物/鉑(TiN/SiGeO/Pt)電阻式記憶體 利用Pulse 電壓
寫入抹除讀取電壓值為0.1V 時電阻值------------------------29
圖 4-1-4 氮化鈦/矽鍺氧化物/鉑(TiN/SiGeO/Pt)電阻式記憶體 做完耐用性測
試後的retention圖-----------------------------------------29
圖4-1-5 氮化鈦/矽鍺氧氮化物/矽鍺氧化物/鉑(TiN/SiGeON/SiGeO/Pt)電阻式記憶體Forming-process 與IV 電性圖。Set 時電流值限制在0.01 安培
-------------------------------------------------------------------30
圖4-1-6 氮化鈦/矽鍺氧化物/矽鍺氧氮化物/矽鍺氧化物/鉑
(TiN /SiGeON/SiGeO/Pt)電阻式記憶體的十萬次endurance 圖
-------------------------------------------------------------------30
圖4-1-7 氮化鈦/矽鍺氧化物/矽鍺氧氮化物/矽鍺氧化物/鉑
(TiN /SiGeON/SiGeO/Pt)電阻式記憶體的一百萬次endurance 圖
-------------------------------------------------------------------31
圖4-1-8 氮化鈦/矽鍺氧氮化物/矽鍺氧化物/鉑(TiN/SiGeON/SiGeO/Pt)電阻式記憶體的做完耐用性測試後retention圖-----------------31
圖4-1-9 氮化鈦/矽鍺氧化物/鉑(TiN/SiGeO/Pt)電阻式記憶體電阻式記憶體100次Set電壓統計圖----------------------------------------32
圖4-1-10 氮化鈦/矽鍺氧氮化物/矽鍺氧化物/鉑(TiN/SiGeON/SiGeO/Pt)電阻式記憶體100次Set電壓統計圖--------------------------------32
圖4-1-11 氮化鈦/矽鍺氧氮化物/矽鍺氧化物/鉑電阻式記憶體不同限制電流進行Set----------------------------------------------------33
圖 4-1-12(a)(b)(c)HRS 各電壓段落 fitting 圖-------------------------33
圖4-1-13(a)(b)(c) MRS 各電壓段落fitting 圖-------------------------34
圖4-1-14(a)(b)(c)LRS 各電壓段落 fitting 圖------------------------34
圖4-1-15 氮化鈦/矽鍺氧氮化物/矽鍺氧化物/鉑電阻式記憶體示意圖-------35
圖4-1-16 單層矽鍺氧試片與矽鍺氧氮/矽鍺氧試片切換示意圖------------35
圖4-2-1 Pulse-IV儀器架接示意圖-------------------------------------38
圖4-2-2 改變DC-sweep間距Reset圖----------------------------------38
圖4-2-3 Pulse IV 量測圖--------------------------------------------40
圖4-2-4 Pulse IV Set電壓與時間關係圖--------------------------------40
圖4-2-5 Pulse IV Reset電壓與時間關係圖------------------------------41
圖4-2-6 PRRAM對時間做積分,電阻式記憶體轉態前,所作功是一個定值。-------41
表目錄
表一 各種次世代非揮發性記憶體優缺點比較-----------------------------6
表二 各種電流的基本傳導過程----------------------------------------17
表三 不同電阻狀態,在不同電壓區段,電流傳導機制比較------------------36
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