本論文描述的編譯器最佳化目標是一個向量基底的單一屬性暫存簇。此最佳化結合了暫存器分配與指令排程。它會在程式執行時去檢驗有純量變數出現的地方，並對其盡可能的最佳化。我們的目標，是將具有相似運算的指令給打包起來，並讓我們的最佳化分配器對它進行優化。
儘管其他研究者也有再進行相似的打包方法，但它們大部分研究都被侷限在硬體上面，硬體通常都會將大量時間耗費在純量暫存器與向量暫存器間的資料搬移。而本篇論文與他們不同的是，我們針對新式硬體架構，不需要在不同屬性的暫存器間做資料搬移，更可以利用硬體特性讓一些純量變數並行運算。因此，我們才能夠取得顯著的加速。
最後，我們所考慮的硬體架構，是正在中山大學開發的GPU嵌入式系統。而此GPU架構裡只有單一暫存簇，並可使用此單一暫存簇來對整數、浮點數、向量，來進行儲存及計算。

This thesis describes a compiler optimization targeted for machines with unified, vector-based register sets. This optimization combines register allocation and instruction scheduling. It examines places where the code performs computations on scalar variables. The goal is to identify instances where the same operation is performed. For example, a program might calculate “base+offset” and then calculate “i+j”. Even though these computations are unrelated, yet they use the same operator; if “base” and “i” are packed into one vector register, while “offset” and “j” are packed into another, then these two computations can be performed simultaneously through the vectors’ parallel addition operation. This would reduce the execution time of the compiled code.
Although other researchers have considered similar packing methods, their work has been limited by the hardware that they were studying. Such hardware usually imposed high costs for moving data between scalar and vector register banks. This present thesis, however, considers a novel hardware architecture that imposes no such costs. As a consequence, we are able to obtain significant speedups.
The architecture that we consider is a Graphics Processing Unit (GPU) for embedded systems that is under development at this university. This GPU has a single register set for integers, float, and vectors.

論文審定書…………………………………… i
摘要 …………………………………….……. ii
Abstract ...............…………………………….iii
Index ……………………………………….….v
1. Introduction 1
2. Basic Concepts 8
2.1 Concepts of Compiler 8
2.1.1 SSA-Form 8
2.1.2 Live Variables 9
2.1.3 Trace Scheduling 9
2.2 How Novel Features in Our GPU Affect the Register Allocator 11
3. Related Work 14
4. Implementation 18
4.1 Machine Code Representation Rewriting 20
4.2 Scheduling and Register Allocation Algorithm 23
5. Experimental Results 29
7. Reference 33
8. Appendix 34

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