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博碩士論文 etd-0629113-155339 詳細資訊
Title page for etd-0629113-155339
論文名稱
Title
使用統計式靜態時序分析,錯誤路徑偵測的機制改善微延遲錯誤測試之效能
Performance Improvement of Small Delay Defects Testing using SSTA and False Path Detection
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
71
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-06-07
繳交日期
Date of Submission
2013-08-21
關鍵字
Keywords
微延遲錯誤、商業自動測試圖樣產生機制工具、統計式靜態時序分析、錯誤路徑、具時序考量的自動測試圖樣產生機制
Commercial ATPG Tool, False Path, Statistical Static Timing Analysis, Timing-aware ATPG, Small Delay Defect
統計
Statistics
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中文摘要
微延遲錯誤(Small Delay Defect, SDD)屬於一種訊號延遲轉態錯誤(Transition Delay Fault, TDF),這種錯誤的延遲時間較短,無法使用傳統的延遲測試機制偵測出。但是這些錯誤所累積的延遲時間,會違反電路的時序限制(Timing Violation),因此有針對微延遲錯誤(Small Delay Defect, SDD)的測試機制。

微延遲錯誤(SDD)通常都是使用商業自動測試圖樣產生機制工具(Commercial ATPG Tools),產生可以檢測微延遲錯誤的測試圖樣(Test pattern)進行檢測。但是由於微延遲錯誤在電路上的數量較多,且每個微延遲錯誤(SDD)的延遲時間過短,在產生自動測試圖樣(ATPG)產生階段必須驅動較多的路徑去產生測試圖樣(Test pattern)偵測,因此需要較多測試圖樣(Test pattern),也需要較多的處理器執行時間(CPU Runtime)。

在商業自動測試圖樣產生機制工具(Commercial ATPG Tools)進行微延遲錯誤(SDD)測試時,必須要搭配靜態時序分析(Static timing analysis, STA)工具進行時序分析產生電路延遲資訊,但是電路上存在著錯誤路徑(False paths)會影響時序分析,使得計算結果較為悲觀,導致不必要的微延遲錯誤(SDD)數量增加。

在這裡提出一套機制,針對時序分析考慮錯誤路徑(False paths)偵測機制,以排除路徑中的錯誤路徑(False paths)和多餘錯誤(Redundant Faults),並改用統計式靜態時序分析(Statistical static timing analysis, SSTA)計算時序,讓時序計算結果更精確,減少微延遲錯誤(SDD)考慮數量,以改進測試圖樣之測試品質(即在一定之錯誤涵蓋率之下減少圖樣數量;或在不增加圖樣數量之下,增加錯誤涵蓋率)以及圖樣數量(Pattern count)。
Abstract
Small Delay Defect (SDD) is one kind of the signal transition delay faults. It could not be detected via traditional delay testing method because the delay time is too small, however, the-se faults could cause timing failure in the circuit when the accumulation of delay time along the paths is too much.

Typical SDD testing uses commercial ATPG Tools, generating SDD test patterns to detect. Since the delay time of SDD is too small, SDD exists too much in the circuit. Thus, SDD has to sensitize more paths to generate SDD test patterns during test pattern generation and too much CPU runtime.

Using commercial ATPG Tools for SDD testing, it has to consider delay information in the circuit by static timing analysis (STA) tools. However, there are false paths in the circuit, which makes delay time calculation much more pessimistic and leads to unnecessary SDDs.

The thesis proposed the method to detect the false paths during timing analysis to exclude the false paths and redundant faults, and meanwhile to apply statistical static timing analysis (SSTA) to calculate timing instead of STA in order to reduce SDD count and pattern count.
目次 Table of Contents
ABSTRACT III
摘要 I
CONTENTS IV
LIST OF FIGURES VI
LIST OF TABLES VII
CHAPTER 1 INTRODUCTION 1
1.1 Background 1
1.2 Motivation 5
1.3 Contribution 5
1.4 Outline 6
CHAPTER 2 PRELIMINARY 7
2.1 Previous Works 7
2.1.1 Faster than at-speed testing 8
2.1.2 Timing-Aware ATPG 8
2.1.3 Pattern Selection 10
2.1.4 Path Selection 12
2.1.5 Other Method 13
2.2 Static Timing Analysis (STA) 13
2.3 Statistical Static Timing Analysis (SSTA) 15
2.4 Criticality of SSTA 16
2.5 Relation between STA and SDD 17
2.6 False Path 17
CHAPTER 3 PROPOSED METHOD 19
3.1 Overall Flow 19
3.2 Problem Definition 20
3.3 Pre-progress: Statistical Static Timing Analysis (SSTA) Preparation 21
3.4 Phase I: Statistical Static Timing Analysis (SSTA) 22
3.5 Phase II: False Path Detection 26
3.6 Phase III: Timing-aware ATPG 30
3.7 Phase IV: Fault Simulation 32
3.8 Algorithm: 35
CHAPTER 4 EXPERIMENTAL RESULT 40
4.1 Environment Setup 40
4.2 Environment Result 40
CHAPTER 5 CONCLUSION & FUTURE WORKS 53
5.1 Conclusion 53
5.2 Future Works 53
REFERENCES 54
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