在本篇論文之中，我們提出了具自我對準與內部阻絕氧化層之電荷捕陷式非揮發性記憶體(Self-Aligned SONOS-type Nonvolatile Memory with Internal Block Oxide, SAIBO-SONOS NVM)。在自我對準技術下將氧化物從SONOS-type NVM之源汲極兩端埋入並輔以乾式蝕刻方式而形成內部阻絕氧化層，之後便完成SAIBO-SONOS NVM。接著以福勒-諾德漢穿隧(Fowler-Nordheim tunneling, FN-tunneling)機制來進行寫入與抹除動作。經由Silvaco TCAD驗證後，相較於無內部阻絕氧化層之電荷捕陷式非揮發性記憶體(SONOS-type NVM without Internal Block Oxide, SONOS NVM)，SAIBO-SONOS NVM都有較佳之非揮發性記憶體之特性。當SAIBO-SONOS NVM寫抹的閘極偏壓為正負14 V時，而且時間都為一秒，寫抹窗口分別改善了16 %與3.3 %，也因此使SAIBO-SONOS NVM之記憶窗口改善了16 %。這是因為內部阻絕氧化層減少了源汲極兩端之電場侵入而改善閘極控制能力。此外資料保持時間特性上，當時間達到十年線時，SAIBO-SONOS NVM之記憶窗口相較於SONOS NVM也改善了50 %。而當閘極持續微縮至40奈米時，SAIBO-SONOS NVM仍然有較佳之寫抹效率與資料保持時間。

In this thesis, we have proposed the self-aligned SONOS-type nonvolatile memory with internal block oxide (SAIBO-SONOS NVM). We use the dry etching method to bury oxide materials from the source/drain (S/D) regions with self-aligned technique to form the internal block oxide structure, and then the SAIBO-SONOS NVM can be finished. Next, program and erase operation can use the Fowler-Nordheim (FN) injection mechanism to carry out. According to the Silvaco simulation results, the SAIBO-SONOS NVM exhibits excellent characteristics compared with the SONOS-type NVM without internal oxide (SONOS NVM). The program/erase (P/E) window of the SAIBO-SONOS NVM can be improved 16 % and 3.3 % with a gate bias of ±14 V for 1 s, respectively. Therefore, its memory window can be improved 16 %. The reason is that the internal block oxide can restrain S/D electric field encroachment, so the gate controllability can be enhanced. In addition, retention time characteristics after ten years for the SAIBO-SONOS NVM can be ameliorated 50 %. Also, as gate length continuously scales down to 40 nm, the SAIBO-SONOS NVM still has better P/E efficiency and retention time.

第一章 緒論 1
1.1 研究背景與重要性 1
1.2 動機與目的 3
1.3 論文架構 6
第二章 非揮發性記憶體之操作機制及其原理 7
2.1 傳統SONOS-type NVM 之介紹 7
2.2 福勒-諾德漢穿隧寫入機制探討 9
2.3 福勒-諾德漢穿隧抹除機制探討 10
2.4 資料保持時間 12
第三章 元件架構設計與製作 14
3.1 元件設計與模擬製程 14
3-1-1 具自我對準與內部阻絕氧化層之奈米元件 14
3-1-2 具自我對準與內部阻絕氧化層之電荷捕陷式非揮發性記憶體 16
3-1-3 無內部阻絕氧化層之奈米元件製程模擬圖 18
3-1-4 無內部阻絕氧化層之電荷捕陷式非揮發性記憶體 19
3.2 元件設計與實際製程 20
3-2-1 具自我對準與內部阻絕氧化層之電荷捕陷式非揮發性記憶體 20
第四章 電性探討與分析 22
4.1 具自我對準與內部阻絕氧化層之奈米元件的使用模型 22
4.2 具自我對準與內部阻絕氧化層之電荷捕陷式非揮發性記憶體的使用模型 23
4.3 具自我對準與內部阻絕氧化層之奈米元件之電性模擬與分析 24
4.4 具自我對準與內部阻絕氧化層之電荷捕陷式非揮發性記憶體之電性分析 27
4-4-1 固定氧化層電荷值與電荷捕陷式非揮發性記憶體之關係 27
4-4-2 SONOS NVM與SAIBO-SONOS NVM之電性探討 32
4-4-3 TANOS NVM與SAIBO-SONOS NVM之電性探討 43
4-4-4 三種不同之電荷捕陷式非揮發性記憶體之電性比較 48
4-4-5 高溫下之資料保持時間特性探討 52
4.5 實作討論與量測結果 53
4.6 SEM與TEM照相與結果討論 58
第五章 總結 62
5.1 結論 62
5-1-1 具自我對準與內部阻絕氧化層之奈米元件 62
5-1-2 SAIBO-SONOS NVM 62
5-1-3 SAIBO-TANOS NVM 63
5-1-4 元件微縮之探討 63
5.2 未來展望 64
參考文獻 65
附錄 70
A.1 通道熱載子注入機制探討 70
A.2 熱電洞注入機制探討 72
A.3 基板暫態熱載子注入 73
A.4 容忍度 74
A.5 干擾 75
A.6 元件模擬設計參數 76
A-6-1 元件設計參數 76
A-6-2 元件材料模擬參數 78
A-6-3 元件製程模擬參數 79
A.7 實作檢討與討論 80
A.8 Study of the SAIBO-SONOS NVM with S/D overlap and underlap 81
附錄參考文獻 84
個人著作 85
共同著作 86

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