ITO為透明導電膜，因具高透光性與良好的導電性，其所應用的範圍有觸控面板、太陽電池、電漿顯示器等。本論文研究應用ITO透明導電薄膜於RRAM上作為電極的特性，製作出一個電阻式記憶體(RRAM)能有效降低功率消耗及操作電壓。實驗利用多靶磁控濺鍍系統製作ITO導電透明電極於SiO2: Gd /TiN 之上形成Metal/Insulator/Metal之RRAM結構，並量測其I-V電性，探討RRAM高低阻態的切換行為。由電性結果發現，Set電壓約為0.2V，Reset電壓約為0.5V，Set與Reset操作電壓有極不對稱的特殊現象，經電流之機制擬合，提出一橢圓空乏區模型解釋。隨後，進行ITO/SiO2: Gd /TiN 樣品照射UV光與紅光影響RRAM特性實驗，比較照光前後，發現低阻值狀態(LRS)的電流機制從未照光前的Schottky emission轉變成照光後Poole-Frenkel 傳導機制。其主因為照光後會使存在於ITO薄膜缺陷中的電子活化，而在缺陷中跳躍。本論文研究set電壓非常小的原因發現其主因為臨界電壓與氧離子濃度梯度兩個因素所影響，且經由改變ITO電極厚度說明與濃度梯度關係。經由Comsol模擬確認ITO電極I-V 曲線的不對稱性。最後基於超臨界二氧化碳超流體(SCCO2)的強氧化能力進行樣品處理，使RRAM的操作電流更下降2.5倍。主因為經SCCO2處理時，經由導入氧離子會修補ITO薄膜中的缺陷，降低RRAM的操作電流及操作功率的消耗。

ITO is a transparent conductive film, owning to high transmittance and good electrical conductivity, ITO has been applied in a wide range over touch panel, solar cell and plasma display. Therefore application of ITO transparent conductive film in resistive random access memory (RRAM) has been studied in this thesis, ITO is promising power consumption inhibitive material in the fabrication of RRAM devices. Meanwhile, operating voltage can be effectively reduced, which makes it possible for the application in stacking memory array. Multi-target magnetron sputtering system is used to deposition ITO/Gd:SiO2/TiN Metal-Insulator-Metal RRAM structure. Besides high and low resistance states of RRAM are investigated by measuring IV electrical curve. Set and Reset operating voltage exhibit asymmetric property, namely Set voltage is about 0.2V and Reset voltage is about 0.5V. Conduction current fitting is applied to explore the reason of the asymmetric voltage, and a model of ellipse depletion region is proposed to explain the abnormal phenomenon. Furthermore, the RRAM property of ITO/SiO2: Gd /TiN sample is measured under UV and red light illumination. Comparing the results obtained before and after light exposure, it is found the low resistance state (LRS) conduction mechanism of the sample transforms from Schottky emission to Poole-Frenkel (after exposure). Due to the activation of defects in ITO film, electrons can hop within the defects. In this work, it is found the ultra-small set voltage results from the combination effects of critical voltage and oxygen ion concentration gradient. Variation the thickness of ITO electrodes is carried out to investigate the influence of oxygen ion concentration gradient. Simulation result by Comsol proves asymmetric property of I-V curve. In addition, the operating current of the device decreases 2.5 times for ITO sample after super critical CO2 (SCCO2) treatment, due to the defects reparation process through the introduction of oxygen from H2O. And the repairing process will facilitate the decrease of RRAM operating current and power consumption.

中文摘要 i
Abstract ii
目錄 iv
圖目錄 viii
表目錄 xi
1-1前言 1
1-2研究目的與動機 2
第二章文獻回顧 3
2-1 記憶體簡介 3
2-2 次世代記憶體簡介 4
2-2-2相變化記憶體【6】 5
2-2-3磁阻式記憶體【8】 6
2-3 絕緣體載子傳導機制 9
2-3-1 穿隧(Tunneling) 10
2-3-2 熱離子發射(Thermionic Emission) 11
2-3-3 普爾-法蘭克發射(Poole-Frenkel Emission) 12
2-3-4 歐姆傳導(Ohmic Conduction) 14
2-3-5 離子電導(Ionic Conduction) 14
2-3-6 空間電荷限制電流(Space Charge Limit Current, SCLC) 15
2-3-7 跳耀傳導(Hopping Conduction)【20】 15
2-4 超臨界流體簡介 16
第三章實驗設備與原理 20
3-1多靶磁控濺鍍系統( Multi-Target Sputter) 20
3-2 N&K薄膜特性分析儀(N & K analyzer) 21
3-3 傅立葉轉換紅外光譜儀 (Fourier-Transform Infrared Spectrometer) 22
3-4 X光光電子能譜儀(X-ray Photoelectron Spectroscopy) 24
3-5半導體電性量測系統 25
3-6 超臨界流體(SCCO2) 26
第四章比較Pt與ITO電極之RRAM結構 28
4-1釓摻雜二氧化矽電阻式記憶體製作流程 28
4-1-1 釓摻雜二氧化矽薄膜備製 29
4-1-2 Pt電極薄膜備製 29
4-1-3 ITO電極薄膜備製 29
4-2釓摻雜二氧化之材料分析 30
4-2-1 FTIR 分析 30
4-2-2 XPS分析 31
4-3 釓摻雜二氧化矽之RRAM電性分析 32
4-3-1 Forming Process： 33
4-3-2 Reset與Set Process 33
4-3-3 記憶保存力(Retention) 34
4-3-4 耐操度(Endurance) 35
4-4 以ITO電極作為釓摻雜二氧化矽電阻式記憶體之電性分析 36
4-4-1 Sample ITO1 RRAM之Forming 過程 36
4-4-2 ITO/Gd:SiO2/TiN RRAM之Set與Reset過程 37
4-4-3 ITO電極作為釓摻雜二氧化矽RRAM Sample之Retention 38
4-4-4 ITO/Gd:SiO2/TiN RRAM之Endurance量測 39
4-4-5 ITO電極與Pt電極作為Gd:SiO2 RRAM可靠度的比較 39
4-5 ITO/Gd:SiO2/TiN電流機制擬合 40
4-6 ITO/Gd:SiO2/TiN傳導機制模型 42
第五章照光對ITO電極RRAM的影響 44
5-1 照射紅光與UV光對元件之影響 44
5-2照射紅光與UV光電流機制擬合 44
5-3 照光環境下傳導機制模型 46
第六章Set電壓與RRAM傳導機制研究 48
6-1 Pt電極與ITO電極I-V曲線比較 48
6-2 Set電壓對RRAM機制研究 49
6-3 Set電壓機制與濃度梯度關係 50
6-3-1 不同厚度ITO電極製程結構 50
6-3-2 ITO自限流Forming Process 51
6-3-3 三種不同厚度ITO電極I-V Curve 52
6-3-4 ITO電極厚度之Set與Reset電壓統計 54
6-3-5 濃度梯度模型說明 56
第七章研究ITO電極I-V 曲線不對稱性 57
7-1 ITO電極不對稱性 57
7-2 Comsol模型模擬 57
第八章ITO/Gd:SiO2/TiN經SCCO2之特性研究 60
8-1 SCCO2處理前備置流程 60
8-2經SCCO2處理的元件結構與實驗參數 60
8-3 SCCO2t處理後ITO電極之材料分析 61
8-4 SCCO2處理後ITO電極之電性分析 67
8-5 SCCO2處理後ITO/Gd:SiO2/TiN RRAM機制模型 72
第九章結論 74
參考文獻 75

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