因應工業綠色環保製程需求傳統IC覆晶技術封裝過程中，焊接的錫球中不可含鉛，故必須在高溫焊接。由於熱漲冷縮之機械應力，造成晶片變形。本論文利用外加機械應力使晶片變形，來研究在不同外加機械應力作用於量測元件下量測分析其電性的傳導機制。其中使用的元件樣品為一個梳狀結構的金屬-絕緣體-金屬(MIM) 電容器樣本，其中有單鑲嵌(SD)及雙鑲嵌(DD)標準工業製程的元件，其金屬導線為銅製程及絕緣層為低介電層(SiOC)結構。
本論文的實驗先將鑲嵌結構的MIM元件，在室溫時由電性測量獲得傳導電流及電容，進而用模具施加應力使得樣本彎曲。在應力作用下量測得受張應力時傳導電流上昇，反之受壓應力時傳導電流下降。另外觀察電容變化得到，隨著張應力增加時電容值會下降，受壓應力增加時電容值會上升。由I-V實驗分析fitting獲得能障差∆Φ及β值。由β來探討對於應力作用下的傳導機制，可得SD的傳導機制為Poole-Frenkel (P-F)的傳導機制，DD的傳導機制符合Schottky emission (SE) 的傳導機制。應力作用影響造成能障的變化，傳導電流受能障的變化而改變。
由C-V實驗結果中得知DD元件中SiOC的電容在壓應力作用時電容上昇，反之張應力作用時電容下降。SD的C-V實驗結果與DD相似，其電容受壓應力作用時上昇，反之張應力作用時下降。因應力作用造成能障的變化，故SD受應力作用的電容變化是受能障的變化的因素。在改變DC Bias的測量時有一個峰值在負電壓位區域處，可得知SD結構的SiOC中有帶正電荷的缺陷存在，且SD是P-F的傳導機制。
DD的電容遠大於SD的電容原因為缺陷能障小於SiOC的能障。在SD中SiOC受張應力與壓應力的能障變化趨勢是一致的，因為電子傳遞於SiC與SiOC的介面缺陷中，其應力作用影響到缺陷的能障變化。而DD的SiOC受張應力作用的能障變化遠大於壓應力作用，可由能障模型解釋之，其與I-V實驗所得之電子傳導行為是一致。

Lead (Pb) free processes have been adopted into Wafer Level Chip Scale Package technology in order to meet the requirements of green environmental production, in which Sn solder without Pb is applied for welding. The welding process performing at the higher temperature will cause thermal and mechanical stress into devices. In this thesis a Metal/Insulator/Metal (MIM) capacitor sample with comb structures is fabricated with low k material of SiOC, single damascene (SD) and dual damascene (DD) structure embedded low resistive Cu for metal connections. A mechanical stress experiment by bending samples is performed to better understand the influence of mechanical stress occurring during Back End Of Line (BEOL) on electronic transport in the SiOC dielectric.
Under compress and tensile stress, the leakage current changes, and becomes higher than unstressed samples for tensile stress, and becomes lower for compress stress. The tensile stress causes to decrease capacitance, and on contrast, compress stress increases capacitance. From the fitting of I-V curve the change of energy barrier ΔΦ and parameter β are obtained. From the value of β yields to the electronic transport in SD to be Poole-Frenkel (P-F) emission, and in DD to be Schottky emission (SE). The variation of leakage current is originated from the energy band barrier change induced by mechanical stress.
The C-V measurement of DD results the increase of capacitance of MIM under compress stress and decrease under tensile stress. The result of SD is similar to DD’s. The capacitance of SD MIM increases under compress stress and decreases under tensile stress, too. It is to conclude the variation of capacitance vs. stress is duo to the energy band barrier change induced by mechanical stress. In addition, SD has a maximum capacitance at negative bias region by sweeping the DC Bias. It indicates that a positive charge of defects existing in dielectric of SD MIM. From the change of capacitance yields the electronic transport in SD to be P-F emission.
The capacitance of DD is much larger than SD's, because its defect energy barrier is less than SiOC energy band barrier. The change of SD capacitance by tensile and compress stress is consistent to the leakage current change through energy barrier change for SiOC of SD due to electron transfer via defects in the interface between SiC and SiOC. Tensile and compress stress affects the energy barrier change of defect by the same mechanism. The energy barrier change of SiOC in DD under tensile stress is much larger than that under compress stress, can be interpreted by the energy barrier model of SE.

Chinese Abstract …………………………………………….. i
English Abstract ……………………………………………. ii
Acknowledgment ……………………………………………. iii
Contents ………………………………………………….... iv
Abbreviations ……………………………………………… vi Table Captions ...……………………………………………… vii
Figure Captions ………………………………………........ viii
Chapter 1 Introduction ………………………………………1
1.1 General Background ……………………………………1
1.2 Experiment Motivation ………………………………...6
1.3 Scheme for Multilevel Interconnect Technologies……...8
Chapter 2 Basic Theory………………………………………15
2.1 Schottky emission Electronic Transport .......................15
2.2 Poole-Frenkel emission Electronic Transport..................19
2.3 Stoney Formula ...............................................................22
Chapter 3 Experimental Procedures ......................................24
3.1 Metal layer structure and dimension parameters of experimental sample.......................................................24
3.2 Wafer Polish experiment procedures .............................27
3.3 Wafer bending experiment procedures ..........................30
3.4 I-V and C-V measurement procedures ............................33
Chapter4 Results and Discussion............................................35
4.1 I-V and C-V Measurement without stress.......................35
4.1.1 DD I-V Electric Characteristics .....................35
4.1.2 SD I-V Electric Characteristics ......................38
4.1.3 C-V Characteristics of DD .................................41
4.1.4 C-V Characteristics of SD .................................42
4.2 I-V Electronic Characteristics under Bending ...............44
4.2.1 Bending I-V Measurement for DD .....................44
4.2.2 Bending I-V Measurement for SD........................53
4.3 C-V Electronic Characteristics under Bending .................62
4.3.1 Bending C-V Measurement for DD.....................62
4.3.2 Bending C-V Measurement for SD ....................65
4.3.3 Bending stress influence energy barrier................68
Chapter 5 Conclusions .............................................................72
References.....................................................................................74
Vita ...............................................................................................82
Publication List ...........................................................................83

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