在本篇論文中，我們為了解決微縮化所遇到的問題，應用本實驗室所提出的新式L型通道之金氧半場效電晶體的架構(Metal Oxide Semiconductor field effect transistor with L-shaped channel structure, L-MOS) [1]，並且針對此概念提出五種通道架構的變化以及應用在電荷捕陷式非揮發性記憶體(SONOS-type Nonvolatile Memory with L-shaped channel structure, L-SONOS)上，達到提高閘極控制能力和降低短通道效應的結果。實驗方法是將傳統單一方向直線式電晶體的通道變為彎曲式，然後探討其通道架構變化時元件的性能以及優缺點。利用熱載子穿隧機制以及福勒-諾德漢穿隧(Fowler-Nordheim tunneling, FN-tunneling)機制來作為記憶體寫入及抹除的操作，並且研究元件辨識窗口(Memory window)、資料保持時間(Retention time)、持久度(Endurance)測試以及汲極干擾(Drain disturb)等課題。
經由 Sentaurus TCAD 驗證過後我們發現，相同本體區尺寸之下 L-MOS 比傳統的MOS元件(Conventional Metal Oxide Semiconductor field effect transistor, Conv-MOS)提升了103 %的輸出電流，以及更強的閘極通道控制能力，且抑制了汲極導致位障降低(Drain-Induced Barrier Lowering, DIBL)效應。除此之外，L-MOS還有更優於傳統MOS 75.8 %的轉導表現和70.9 %的電壓增益表現。
接著，我們探討L-SONOS在非揮發性記憶體的表現。因為L型通道架構的特殊性，使得閘極控制能力提升，導致元件辨識窗口大幅的增加了50.89 %。加上彎曲通道的因素，使得源極與汲極兩端較無直接的電場作用影響，讓資料的保持時間得以延長。且在汲極干擾抑制能力的表現上相較傳統元件的衰退(65.3 %)，L-SONOS只衰退了38.9 %。而L-SONOS元件雖然在持久度的表現上稍微比Conv-SONOS來的差，但整體表現上來說L-SONOS還是一個性能表現優於傳統架構的記憶體元件。

In this paper, in order to overcome the scale down issue, a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (L-MOS) [1], and new L-shaped channel structure for SONOS-type nonvolatile memory (L-SONOS) are designed and studied. Besides, the several types of L-shaped structures are also demonstrated. Meanwhile, we use Fowler-Nordheim tunneling (FN tunneling) mechanism for memory's program and erase, and analyses the memory window, retention time, endurance, and drain disturb.
Studied and compared with the conventional MOSFET device for the same average gate length (Lavg), the proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) Sentaurus TCAD simulators. It can be confirmed that the L-MOS device's drain current(ID) have been improved more than 103 % as compared to that of Conv-MOS andthe device has lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the L-MOS are also improved 75.8 % and 70.9 % than its counterpart.
In addition, we analyze the electrical characteristics of the L-SONOS. Because of the L-shaped channel structure, L-SONOS reveals a better gate controllability. The memory window of it improves 50.89 % compare with Conv-SONOS, and better retention time performance has been seen. In addition, the Vth shift at drain disturb performance of the new device only falls 38.9 % compare to 65.3 % of the conventional device(Conv-SONOS) does. Although the L-SONOS's endurance performance is lower than conventional one, the overall performance of the L-SONOS still can be said that it is a better SONOS memory device than its counterpart, Conv-SONOS.

第一章 導論 1
1.1 研究背景與重要性 1
1.2 國內外研究探討 3
1.3 動機與目的 7
1.4 論文架構 8
第二章 元件操作機制與原理 9
2.1 MOSFET元件探討 9
2.1.1 MOSFET元件基本介紹 9
2.1.2 MOSFET微縮化探討 11
2.2 SONOS元件探討 11
2.2.1 SONOS元件基本介紹 11
2.2.2 熱載子寫入和熱電洞抹除機制 13
2.2.3 福勒-諾德漢穿隧寫入與抹除機制 28
2.2.4 資料保持時間與耐久度 28
第三章 元件設計與製程 19
3.1 具有L型通道架構的金氧半場效電晶體 19
3.1.1 元件模擬設計 19
3.1.2 元件實際製程 21
3.2 具有L型通道架構的金氧半場效電晶體應用在電荷捕陷式非揮發性記憶體 23
3.2.1 元件模擬設計 23
3.2.2 元件實際製程 25
第四章 研究方法與電性分析 27
4.1 具有L型通道架構的金氧半場效電晶體之使用模型 27
4.2 具有L型通道架構的金氧半場效電晶體應用在電荷捕陷式非揮發性記憶體之使用模型 28
4.3 具有L型通道架構的金氧半場效電晶體之電性模擬與分析 30
4.4 具有L型通道架構的金氧半場效電晶體應用在電荷捕陷式非揮發性記憶體之電性模擬與分析 37
4.5 L-SONOS之微縮化電性模擬與分析 49
4.6 Isolation last製程之L-SONOS的電性模擬與分析 63
4.7 實作討論與量測數據 67
第五章 結論與未來展望 70
5.1 結論 70
5.2 未來展望 72
參考文獻 73
附錄 78
論文著述 80

[1] P.-H. Lin, and J.-T. Lin, “Characterization of a New L-Shaped MOSFET for Future Deca Nano Application,” in Proc. 28th Int. Conf. on Microelectronics, May 2002, pp. 221－224.
[2] X. Sun, and T.-J. K. Liu, “Scale-Length Assessment of the Trigate Bulk MOSFET Design,” IEEE Trans. Electron Devices, vol. 56, no 11, pp. 2840－2842, Nov. 2009.
[3] R. A. Vega, and T.-J. K. Liu, “Three-Dimensional FinFET Source/Drain and Contact Design Optimization Study, ” IEEE Trans. Electron Devices, vol. 56, no 7, pp. 1483－1492, Jul. 2009.
[4] B. Ramadout, G.-N. Lu, J.-P. Carrere, L. Pinzelli, C. Perrot, M. Rivoire, and F. Nemouchi, “Multigate MOSFET in a Bulk Technology by Integrating Polysilicon-Filled Trenches,” IEEE Electron Device Lett., vol. 30, no 12, pp. 1350－1352, Dec. 2009.
[5] P. Magnone, A. Mercha, V. Subramanian, P. Parvais, N. Collaert, M. Dehan, S. Decoutere, G. Groeseneken, J. Benson, T. Merelle, R. J. P. Lander, F. Crupi, and C. Pace, “Matching Performance of FinFET Devices With Fin Widths Down to 10 nm,” IEEE Electron Device Lett., vol. 30. no 12, pp. 1374－1376, Dec. 2009.
[6] D. Temmler, “Silicon on insulator technologies and devices from present to future,” Laboratoire de Physique des Composants a Semiconducteurs (UA-CN RS & INPG), ENSERG, B.P. 257, 38016 Grenoble Cedex 1, France, Mar. 2000.
[7] M. Ieong, H.-S. P. Wong, E. Nowak, J. Kedzierski, and E. C. Jones, “High Performance Double-Gate Device Technology Challenges and Opportunities,” In Proc. IEEE Int. Symp. on Quality Electronic Design, 2002, pp. 492－495.
[8] G. Leung, and C. O. Chui, “Variability of Inversion-Mode and Junctionless FinFETs due to Line Edge Roughness,” IEEE Electron Devices Lett., vol. 32, no. 11, pp. 1489－1491, Nov. 2011.
[9] F. Udrea, A. Popescu, and W. Milne, “Breakdown analysis in JI, SOI and partial SOI power structures,” in Proc. IEEE Int. SOI Conf., Oct. 1997, pp. 102－103.
[10] S. Gundapaneni, S. Ganguly, and A. Kottantharayil, “Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling,” IEEE Electron Devices Lett., vol. 32, no. 3, pp. 261－263, Mar. 2011.
[11] C. W. Oh, S. H. Kim, D.-W. Kim, D. Park, and K. Kim, “Hybrid Integration of Ultrathin-Body Partially Insulated MOSFETs and a Bulk MOSFET for Better IC Performance: A Multiple-VTH Technology Using Partial SOI Structure,” IEEE Electron Devices Lett., vol. 31, no. 1, pp. 59－61, Jan. 2010.
[12] H. Ye, W. Su, B. Zhang, Z. J. Li, and M. Qiao, “High Figure-of-merit Vertical Double Diffused MOSFET with the Charge Trenches on Partial SOI,” in Proc. IEEE Asia Pacific Conf. on Postgraduate Research in Microelectronics and Electronics, Jan. 2009, pp. 137－140.
[13] S. A. Loan, S. Qureshi, and S. S. K. Iyer, “Lateral Bipolar Transistor on Partial SOI: a 2D Simulation Study,” in Proc. IEEE Saudi Int. Electronics, Communications and Photonics Conf., Apr. 2011, pp. 1－4.
[14] A. Singh, and A. K. Chatterjee, “Study of Ground Plane FD SOI Structures at 25 nm,” in Proc. IEEE Int. Conf. on Nanoscience, Engineering and Tech., Nov. 2011, pp. 187－189.
[15] H.-W. Cheng, and Y. Li, “16-nm Multigate and Multifin MOSFET Device and SRAM Circuits,” Int. Journal of Electrical Engineering, vol. 18, no. 6, pp. 277－283, Dec. 2011.
[16] C.-Y. Chang et al., “A 25-nm Gate-Length FinFET Transistor Module for 32nm Node,” in Proc. Int. Electron Devices Meeting, Dec. 2009, pp. 12.2.1－12.2.4.
[17] Y. Li and C.-H. Hwang, “Effect of Fin Angle on Electrical Characteristics of Nanoscale Round-Top-Gate Bulk FinFETs,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3426－3429, Dec. 2007.
[18] H.-W. Cheng, C.-H. Hwang, and Y. Li, “Propagation Delay Dependence on Channel Fins and Geometry Aspect Ratio of 16-nm Multi-Gate MOSFET Inverter,” in Proc. Asia Symp. on Quality Electronic Design, Jul. 2009, pp. 122－125.
[19] V. V. Iyengar, A. Kottantharayil, F. M. Tranjan, M. Jurczak, and K. D. Meyer, “Extraction of the Top and Sidewall Mobility in FinFETs and the Impact of Fin-Patterning Processes and Gate Dielectrics on Mobility,” IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1177－1184, May 2007.
[20] A. Malinowski, A. Kociubinski, P. Salek, L. Lukasiak, M. Zaborowsai, D. Tomaszewski, and A. Jakubowski, “ELECTRICAL CHARACTERIZATION OF FINFETS,” in Proc. of The 15th Int. Conf. Mixed Design of Integr. Circuits and Systems, Jun. 2008, pp. 65－69.
[21] T. Rudenko, V. Kilchytska, N. Collaert, M. Jurczak, A. Nazarov, and D. Flandre, “Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities,” IEEE Trans. Electron Devices, vol. 55, no. 12, pp. 3532－3541, Dec. 2008.
[22] T.-Y. Chiang, William C.-Y. Ma, Y.-H. Wu, K.-T. Wang, and T.-S. Chao, “A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals,” IEEE Trans. Electron Devices, vol. 31, no. 11, pp. 1239－1241, Nov. 2010.
[23] J.-W. Han, S.-W. Ryu, S. Kim, C.-J. Kim, J.-H. Ahn, S.-J. Choi, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “A Bulk FinFET Unified-RAM (URAM) Cell for Multifunctioning NVM and Capacitorless 1T-DRAM,” IEEE Electron Devices Lett., vol. 29, no. 6, pp. 632－634, Jun. 2008.
[24] C.M.R. Prabhu, and A. K. Singh, “Low-Power Fast Static Random Access Memory Cell,” Int. Conf. on Computer Applications and Industrial Electronics (ICCAIE 2010), Dec. 2010, pp. 5－8.
[25] S. Lee, J. S. Shin, J. Jang, H. Bae, D. Yun, J. Lee, D.H. Kim, and D.M. Kim, “A Novel Capacitorless DRAM Cell Using Superlattice Bandgap-Engineered (SBE) Structure With 30-nm Channel Length,” IEEE Trans. Nanotechnology, vol. 10, no. 5, pp. 1023－1030, Sep. 2011.
[26] H. Eawagoe, and N. Tsuji, “MINIMUM SIZE ROM STRUCTURE COMPATIBLE TO SILICON GATE E/D MOS LSI,” IEEE Solid State Circuits Conf., Sep. 1975, pp. 111－112.
[27] G. Gear, “FAMOS PROM RELIABILITY STUDIES,” IEEE Reliability Physics Symp., Apr. 1976, pp. 198－201.
[28] H. Pein, and J. D. Plummer, “A 3D sidewall flash EPROM cell and memory array,” IEEE Trans. Electron Devices, vol. 40, no 11, pp. 2126－2127, Nov. 1993.
[29] H. J. Mattausch, H. Baumgärtner, R. Allinger, M. Kerber, and H. Braun, “Electrical/Thermal Properties of Nonplanar Polyoxides and the Consequent Effects for EEPROM Cell Operation,” IEEE Trans. Electron Devices, vol. 47, no. 6, pp. 1251－1257, Jun. 2000.
[30] G. Zhang, W.J. Yoo, and C.-H. Ling, “Hot-Electron Capture for CHEI Programming in SONOS-Type Flash Memory Using High-k Trapping Layer,” IEEE Trans. Electron Devices, vol. 55, no. 6, pp. 1502－1510, Jun. 2008.
[31] S. I. Shim, F. C. Yeh, X. W. Wang, and T. P. Ma, “SONOS-Type Flash Memory Cell With Metal/Al2O3/SiN/Si3N4/Si Structure for Low-Voltage High-Speed Program/Erase Operation,” IEEE Electron Device Lett., vol. 29. no 5, pp. 512－514, May 2008.
[32] L. Larcher, P. Pavan, S. Pietri, L. Albani, and A. Marmiroli, “A New Compact DC Model of Floating Gate Memory Cells Without Capacitive Coupling Coefficients,” IEEE Tran. Electron Devices, vol. 49, no. 2, pp. 301－307, Feb. 2002.
[33] B. Sarkar, N. Ramanan, S. Jayanti, N. D. Spigna, B. Lee, P. Franzon, and V. Misra, “Dual Floating Gate Unified Memory MOSFET With Simultaneous Dynamic and Non-Volatile Operation,” IEEE Electron Device Lett., vol. 35. no 1, pp. 48－50, Jan. 2014.
[34] P. B. Kumar, P. R. Nair, R. Sharma, S. Kamohara, and S. Mahapatra, “Lateral Profiling of Trapped Charge in SONOS Flash EEPROMs Programmed Using CHE Injection,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 698－705, Apr. 2006.
[35] G. S. Lee, J. H. Lee, I. H. Park, S. Cho, J.-G. Yun, D. H. Li, D. H. Kim, Y. Kim, S. H. Park, W. B. Shim, W. D. Kim, J. D. Lee, H. Shin, and B.-G. Park, “Cone-Type SONOS Flash Memory,” IEEE Electron Device Lett., vol. 30. no 12, pp. 1332－1334, Dec. 2009.
[36] X. Zhou, H. Feng, and J. K.O. Sin, “Hot Carrier Injection Effects in the Ultrashallow Body SONOS Gate Power MOSFET,” IEEE Trans. Electron Devices, vol. 60, no. 6, pp. 2008－2014, Jun. 2013.
[37] G. V. d. bosch, G. S. Kar, P. Blomme, A. Arreghini, A. Cacciato, L. Breuil, A. D. Keersgieter, V. Paraschiv, C. Vrancken, B. Douhard, O. Richard, S. V. Aerde, I. Debusschere, and J. V. Houdt, “Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D NAND Flash Memory,” IEEE Electron Device Lett., vol. 32. no 11, pp. 1501－1503, Nov. 2011.
[38] S.-C. Tseng, J-T Lin , and S-W Hsu, “An Investigation of the SONOS with Side-Block Oxide for Non-Volatile Memory,” IEEE Conf. in Bursa, Nov. 2013, pp. 390－392.
[39] G.-W. Chang, T.-C. Chang, Y.-E. Syu, Y.-H. Tai, and F.-Y. Jian, “On-Current Decrease After Erasing Operation in the Nonvolatile Memory Device With LDD Structure,” IEEE Electron Device Lett., vol. 32. no 8, pp. 1038－1040, Aug. 2011.
[40] A. Arreghini, G. S. Kar, G. V. d. bosch, and J. V. Houdt, “Impact of Charge Trapping Layer Thickness and New Trade-Off in Performance Characteristics of 3-D SONOS Devices,” IEEE Electron Device Lett., vol. 34. no 5, pp. 632－634, May 2013.
[41] B.-Y. Tsui, C.-C. Yen, P.-H. Li, and J.-Y. Lai, “Effects of EUV Irradiation on Poly-Si SONOS NVM Devices,” IEEE Electron Device Lett., vol. 32. no 5, pp. 614－616, May 2011.
[42] S.-H. Gu, C.-W. Hsu, T. Wang, W.-P. Lu, Y.-H. J. Ku, and C.-Y. Lu, “Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells,” IEEE Trans. Electron Devices, vol. 54, no 1, pp. 90－97, Jan. 2007.
[43] S.-Y. Wang, H.-T. Lue, P.-Y. Du, C.-W. Liao, E.-K. Lai, S.-C. Lai, L.-W. Yang, T. Yang, K.-C. Chen, J. Gong, K.-Y. Hsieh, R. Liu, and C.-Y Lu, “Reliability and Processing Effects of Bandgap-Engineered SONOS (BE-SONOS) Flash Memory and Study of the Gate-Stack Scaling Capability,” IEEE Trans. Electron Devices and Materials Reliability, vol. 8, no 2, pp. 416－425, Jun. 2008.
[44] D. Kaba, T. C. Chien, C. B. Jiew, S. Sewoon, “The Development of an Enhancement-Mode Single-Transistor SONOS Cell in 0.13μm Technology,” in 3rd Asia Symp. on Quality Electronic Design, Jul. 2011, pp. 292－295.
[45] Y.-H. Koh, J.-H. Choi, M.-H. Nam, and J.-W. Yang, “Body-Contacted SOI MOSFET Structure with Fully Bulk CMOS Compatible Layout and Process,” IEEE Electron Device Lett., vol. 18. no 3, pp. 102－104, Mar. 1997.
[46] S. M. Sze, “Semiconductor Devices Physics and Technology,” 2nd ed., New Jersey: Wiley, pp. 172, 2001.
[47] M. H. White, Y. (Richard) Wang, S. J. Wrazien, Y. (Sandy) Zhao, “Advancement in Nanoelectronic SONOS Nonvolatile Semiconductor Memory (NVSM) Devices and Technology*,” Int. Journal of High Speed Electronics and Systems, vol. 16, No. 2, pp. 479－501, 2006.