在函數求值運算的硬體設計領域當中，查表相加方法是基於多個查表儲存所需內容，並輸入一多源輸入加法器，以得到最後運算結果，例如multipartite table設計[3]，此類方法無需使用乘法器，延遲較少，但由於表格隨精準度提升而成長過大，造成此方法多使用於低精準度應用，本論文提出表格分解方法，將園方法中儲存初始值得一個表格，由兩到三個面積較小的新表格所取代，以降低表格面積。實驗結果顯示，相較於目前最佳的multiaprtite查表相加設計[3]，本論文所提出的方法可有效降低表格面積。

In hardware design of the elementary function evaluation, Table-lookup-and-addition method is a category of multiplier-less method, based on several lookup tables and a multi-operand adder to calculate the final function value. Multipartite table method [3] is a popular multiplierless function evaluation design. These multiplierless methods usually have small delay but the table size grows very fast with respect to accuracy .Thus they are only used in applications with low-precision requirements. In this thesis, new table decomposition methods are proposed in order to reduce table size in the multipartite design. The original table is decomposed into two or three smaller tables so that the total table size is efficiently reduced. Experimental results show that the proposed design can significantly reduce the bit count of the tables for different functions compared with the multipartite methods in [3] which is the best table-addition method reported so far.

[CHAPTER1導論1]
[1.1研究動機1]
[1.2論文架構2]
[CHAPTER2研究背景與相關研究3]
[2.1表格為主無乘法器方法數學原理3]
[2.2BIPARTITE函數運算方法介紹4]
[2.3SYMMETRIC BIPARTITE函數運算方法7]
[2.4MULTIPARTITE函數運算方法11]
[2.5壓縮樹設計15]
[CHAPTER 3MULTIPARTITE初始值表格拆解方法16]
[3.1TWO TABLE初始值表格拆解原理16]
[3.2 THREE TABLE初始值表格拆解設計原理20]
[3.3 參數優化演算法23]
[CHAPTER 4 實驗數據比較26]
[4.1 位元數計算比較27]
[4.2 參數優化數據比較41]
[4.3 合成數據比較46]
[4.4 與UNIFORM PIECEWISE函數逼近法比較49]
[CHAPTER 5 結論與未來展望52]

[1] J.-M. Muller, “A Few Results on Table-Based Methods,” Reliable Computing, vol. 5, pp. 279-288, 1999.
[2] J. Stine and M. J. Schulte, “The Symmetric Table Addition Method for Accurate Function Evaluation,” Journal VLSI Signal Processing, vol. 21, pp. 167-177, 1999.
[3] F. de Dinechin and A. Tisserand, “Multipartite Table Methods,” IEEE Trans. Computers, vol. 54, no. 3, pp. 319-330, Mar. 2005.
[4] H.-J. Ko and S.-F. Hsiao, "Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 58, no. 5, pp. 304-308, May 2011.
Yu-Ling Tseng and Dr. Shen-Fu Hsiao, “ Design of a Table-Driven Function Evaluation Generator Using Bit-Level Truncation Methods
使用位元截斷法之查表示函數求值單元自動產生器設計”, 國立中山大學資訊工程學系碩士論文 2011
[5] B.-G. Nam, H. Kim and H.-J. Yoo, “Power and Area-Efficient Unfied Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems,” IEEE Trans. Computers, Vol. 57, No. 4, pp. 490-504, Apr. 2008.
[6] D. De Caro, N. Petra, and A. G. M. Strollo, “High-Performance Special Function Unit for Programmable 3-D Graphics Processors,” IEEE Trans. Circuits and Systems-I, Vol. 56, No. 9, pp. 1968-1978, Sept. 2009.
[7] Y.-J. Kim, et al., “Homogeneous Stream Processors with Embedded Special Function Units for High-Utilization Programmable Shaders,” IEEE Trans. VLSI Systems, vol. 20, no. 9, pp. 1691-1704, Sept. 2012.
[8] D. Das Sarma and D. Matula, “Faithful Bipartite ROM Reciprocal Tables,” Proc. 12th IEEE Symp. Computer Arithmetic, S. Knowles and W. McAllister, eds., pp. 17-28, 1995.
[9] M. Schulte and J. Stine. “Symmetric bipartite tables for accurate function approximation.”in Proceedings of the 13th IEEE Symposium on Computer Arithmetic, 1997.
[10] D. De Caro, N. Petra, and A. G. M. Strollo, “Reducing lookup-table size in direct digital frequency synthesizers using optimized multipartite table method,” IEEE Trans. Circuits Syst. I, vol. 55, no. 7, pp.2116–2127, Aug. 2008.
[11] D-U Lee, R.C.C Cheung, W. Luk, and J.D. Villasenor, “Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations,” IEEE Transactions on Computers, vol. 57, no. 5, pp. 686-701, May 2008.
[12] F-d Dinechin and A. Tisserand, “Some Improvements on Multipartite Table Methods,” Proc. 15th IEEE Symp. Computer Arithmetic, pp. 128-135, 2001.
[13] J.A. Pineiro, J.M. Muller, and J.D. Bruguera, “High-Speed Function Approximation Using a Minimax Quadratic Interpolator,” IEEE Transactions on Computers, vol. 54, no. 3, pp. 304-318, Mar. 2005.
[14] Davide De Caro, Nicola Petra, and Antonio G. M. Strollo, “High-Performance Special Function Unit for Programmable 3-D Graphics Processors,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 9, pp. 1968-1978, SEPTEMBER 2009
[15] D-U Lee, W. Luk, J. Villasenor, and P.Y.K. Cheung, “Non-uniform Segmentation for Hardware Function Evaluation,” Proc. 11th Int’l Conf. Field Proframmable Logic and Applications, pp. 796-807, Sept. 2003.
[16] M. J. Schulte and E. E. Swartzlander Jr, “Truncated multiplication with correction constant,” VLSI Signal Processing VI, pp. 388 - 396, 20-22 Oct. 1993.
[17] 黃文良, “以查表為主之函數運算的表格面積縮減方法,” 國立中山大學資訊工程學系碩士論文,2010.