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博碩士論文 etd-0631113-135814 詳細資訊
Title page for etd-0631113-135814
論文名稱
Title
新穎垂直式高集積薄膜互補金氧半技術之研究
Study of a Novel High-Integration Vertical TFT-CMOS Technology
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
94
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-18
繳交日期
Date of Submission
2013-08-07
關鍵字
Keywords
源極-體極接面與閘極控制區重疊、埋入式氧化層、集積密度、平均傳輸延遲、垂直架構
packing density, vertical structure, buried oxide, propagation delay time, source overlap
統計
Statistics
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The thesis/dissertation has been browsed 5663 times, has been downloaded 1263 times.
中文摘要
在本論文中,我們提出一個高集積密度、製程步驟簡單之新穎互補式金氧半(Novel CMOS)反相器,此種新穎互補式金氧半反相器是利用垂直架構電晶體(Vertical transistor)取代原本平面傳統互補式金氧半(CMOS)反相器,以提升集積密度(Packing density)。在論文中主要是探討垂直式金氧半反相器的特性分析。
根據結果,本論文提出的非傳統互補式金氧半反相器有正確的邏輯特性,平均傳輸延遲與平面式金氧半反相器比較改善40 %,這是因為此非傳統互補金氧半反相器是使用源極-體極接面與閘極控制區重疊(Source overlap)使驅動電流增強了21 %,和汲極接面遠離閘極控制區(Drain underlap)降低寄生電容18 %的緣故。在製程上,利用斜角離子佈值,所以不需要有額外的光罩即可形成正型金氧半場(PMOS)與負型金氧半(NMOS),並且達到源極-體極接面與閘極控制區重疊、汲極與體極接面遠離閘極控制區。在佈局面積上,此垂直式互補式金氧半反相器與傳統互補式金氧半反相器比較在佈局面積上可以減少47.4 %,可提升元件的集積密度。
Abstract
In this thesis, we present a novel CMOS inverter with simple process and high integration density. The novel CMOS inverter exploit vertical transistor can improve packing density, when compared with the planar CMOS inverter. We focus on the investigation of novel vertical TFT-CMOS trends. In addition, we also design a planar CMOS for comparison.
According to the simulations, the logical characteristics of our proposed CMOS are valid, in which the average propagation delay time is improved 40 % compared with the planar CMOS. That are due to the ION is improved 21 % with the source overlap and the parasitic capacitance is improved 18 % with the drain underlap. The scheme employs a clever tilted-angle implant process in the fabrication; therefore, both p-channel and n-channel devices require only one lithographic step to form the source overlap and drain underlap. The layout area can be significantly decreased 47.4 %, in comparison with the conventional CMOS.
目次 Table of Contents
第一章 緒論 1
1.1 背景 1
1.2 動機 4
第二章 元件物理機制與設計 6
2.1 物理機制 6
2.1.1 源極-體極接面與閘極控制區重疊 6
2.1.2 汲極-體極接面與閘極控制區無重疊且遠離閘極控制區 9
2.1.3 汲極和源極空間電荷區 11
2.2 元件操作原理與比較 13
2.2.1 傳統互補式金氧半反相器架構和操作原理 13
2.2.2 垂直式互補金氧半反相器操作原理 16
2.2.3 比較垂直式互補金氧半反相器與平面式互補金氧半反相器 19
第三章 元件架構設計與製程步驟 23
3.1 元件設計 23
3.2 模擬製程步驟 24
3.3 模擬實際製程架構 26
3.3.1 模擬實際製程垂直式薄膜互補金氧半反相器 26
第四章 結果與討論 28
4.1 元件模擬使用之物理模型 28
4.2 元件模擬電性結果之分析與討論 29
4.2.1 比較在不同閘極長度的垂直式薄膜互補金氧半 29
4.2.2 改變閘極長度之垂直式互補金氧半反相器評量指標(FOM) 34
4.2.3 比較在不同柱狀氧化層寬度的垂直式薄膜互補金氧半 35
4.2.4 改變柱狀氧化層寬度之垂直式互補金氧半反相器評量指標 39
4.3 邏輯電路模擬 40
4.3.1 反及閘 (NAND Gate) 40
4.3.2 反或閘(NOR Gate) 46
4.3.3 互斥或閘 (XOR) 52
4.3.4 全加器 (Full Adder) 54
4.3.5 環形振盪器 (Ring Counter) 56
4.4 佈局 (Layout)比較 57
4.5 實際垂直式互補金氧半反相器電性 59
第五章 結論與未來展望 65
5.1 結論 65
5.2 未來展望 66
參考文獻 67
附 錄 73
A.1 PMOS & N+N N+ VCMOS 73
A.2 P+PP+ & NMOS VCMOS與 PMOS & N+N N+ VCMOS比較 74
A.3 P+PP+ & NMOS VCMOS與 PMOS & N+N N+ VCMOS的評量指標(FOM) 77
個人著作 79
共同著作 80
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