近年來，隨著高科技世代的演進，平面顯示器產業快速發展，廣泛的應用於消費性電子產品，如高解析度電視、筆記型電腦、數位相機與智慧型資訊產品。薄膜電晶體扮演著電流驅動與控制畫素開關之關鍵元件，薄膜電晶體的電性表現與穩定度將直接影響平面顯示器的品質。金屬氧化物薄膜電晶體擁有高載子移動率、高均勻性、透明與低製程溫度之特性，近年來吸引許多研究單位的投入並獲得產業界高度的關注；然而，金屬氧化物薄膜電晶體於環境之不穩定性，使得元件在實際畫素陣列電路操作下容易被外在環境與操作電壓而產生劣化行為，因此釐清物理機制與電性可靠度分析之方法成為下一世代顯示器之重要知識與技術。
本論文第一部分探討了氧化物銦鎵鋅氧(InGaZnO)薄膜電晶體於真實操作下將會面臨之環境溫度效應。實驗結果顯示外界環境溫度的上升，高溫環境使熱激發電洞形成，而汲極電場將使熱激發的電洞聚積於源極端並造成源極端能障下降，導致嚴重次臨界延伸電流的形成，透過升溫的電容-電壓量測可以證實熱激發(缺陷輔助)電洞的形成；利用二氧化氮電漿進行銦鎵鋅氧薄膜(InGaZnO)的優化處理，能提升薄膜電晶體於高溫狀態下的電性可靠度，進行了處理前後點缺陷密度的計算。
第二部分吾人討論氧化物銦鎵鋅氧(InGaZnO)薄膜電晶體於濕氣環境下之閘極偏壓電應力操作下之穩定性與可靠度分析。於閘極負偏壓施加的狀態下，環境極性水分子由於垂直電場影響吸附於保護層的表面，產生水合反應生成質子(H+)，質子透過孤對電子對傳輸直到與主動層的電子達成電荷平衡；於保護層表面之負電荷氫氧根離子(OH-)對裸露區能帶造成額外的能障抬昇，導致臨界電壓往正閘極方向漂移的現象；質子傳輸造成閘極-通道電容電壓量測曲線有兩階段抬昇的現象，我們可以知道電容的兩階段現象是受裸露區OH-離子造成的能帶抬昇所導致。藉由變動閘極電應力施加後，臨界電壓飄移與恢復機制的量測手法，驗證了質子傳輸機制模型。
第三部分探討閘極負偏壓紫外光照光環境電應力(NBIS)操作對銦鎵鋅氧(InGaZnO)薄膜電晶體的臨界電壓飄移現象。NBIS操作下同時施加汲極電壓，可以觀察到次臨界電流延伸的情況產生，這是由於橫向電場將令紫外光光照形成的電洞往源極端聚積，由改變電流方向的電流電壓量測搭配變溫萃取熱場發射的活化能，並且量測電容電壓曲線驗證了電洞不對稱的分布狀態。利用傳輸線方法(Transmission Line Method)萃取出各對應電壓與施加應力時間的接觸電阻，得知橫向電場的施加，將使接觸電阻下降，間接說明電洞聚積引起的源極能障下降，我們更能換算各對應汲極電應力之有效的通道長度。
最後，我們討論了銦鎵鋅氧(InGaZnO)薄膜電晶體的熱載子效應，蝕刻終止層的接觸窗口型元件會因為源極和汲極之多餘電極會導致電子注入於汲極多餘電及下方的通道蝕刻終止層中，且這些注入之電子會侷限在多餘電極的位置，這樣的電子注入狀態造成閘極-源極電容曲線有兩階段抬升的現象。透過量測不同的電極金屬材料，可得知電子注入於蝕刻終止層中所需的熱場發射活化能與金屬材料的功函數有對應的關係。

In recent years, along with the evolution of high-tech generation and rapid development of flat panel display industry, widely used in consumer electronic products, such as high resolution TV, notebook computers, digital cameras and intelligent information products. Thin film transistor plays current drive and control pixel switch key components, thin film transistor electrical performance and stability will directly affect the quality of flat panel display. Metal oxide thin film transistor has high load moving rate, high uniformity, transparency and low process temperature characteristics, in recent years to attract investment in many research institutes and received highly attention in the circle of industry; however, metal oxide thin film transistors on instability of environment, the components in the actual operation of pixel array circuit is easy to external environment and operating voltage and degradation behavior. Therefore, to clarify the physical mechanism and electric reliability degree analysis method become the next generation display is the importance of knowledge and technology.
The first part discusses the indium gallium zinc oxide oxygen InGaZnO thin film transistor in the real operation, will face the effect of environmental temperature. Experimental results show rise in ambient temperature, high temperature environment, the thermal excitation electric hole formation, and drain pole electric field will make thermal excitation electric hole accumulation on extreme and cause source extreme can avoidance decreased, resulting in serious time critical extension of the current formation, through heating the capacitance voltage measurement can confirm the thermal excitation (defect assisted electric hole formation; the use of nitrogen dioxide plasma processing optimization of indium gallium zinc oxide thin film (InGaZnO), can enhance thin film transistors for high temperature electrical reliability, before and after the treatment of point defect density calculation.
In the second part, we studies the operation stability and reliability analysis of InGaZnO thin film transistors indium gallium zinc oxide oxygen moisture environment for the gate bias electric stress. Cause is to reach through the surface of the water molecules in a gate bias voltage is applied to the state, the environment polarity due to the vertical electric field influence on the adsorption on protective layer, resulting in the hydration reaction to generate protons (H+), proton lone pair of electrons on the transmission until the active layer of electronic charge balance; in protective layer surface negative charge hydroxyl ions (OH-) on the exposed area with causing additional energy barrier uplift, leading to critical voltage gate drift phenomenon; proton transfer gate to channel capacitance voltage measurement curve has two stages uplift phenomenon, we can know the capacitance of two stage phenomenon is subject to the exposed area of OH - ions caused by the uplift of lead. By changing gate electric stress is applied, the critical voltage drift and recovery mechanisms quantity measurement technique, the proton transfer mechanism model was verified.
The third part discuss gate very negative bias UV illumination electrical environment should be NBIS operation of indium gallium zinc oxide (InGaZnO) thin film transistor threshold voltage drift phenomenon. NBIS operation under the simultaneously applied drain bias voltage, can be observed extending time critical current generation. This is due to transverse electric field will enable the UV light electric hole formation to the source extreme accumulation, by changing the current direction of current and voltage measurement match temperature swing extraction thermal field emission activation energy and measurement capacitance voltage curve to verify the distribution state of imbalance. Using the transmission line method (transmission line method to extract out the corresponding voltage and applied the contact resistance and that transverse electric field is applied, will make the contact resistance decreased, indirectly, that the electric hole accumulation caused by source lower barriers, we can better conversion to the corresponding drain electrode should be the effective channel length.

Finally, we discuss the indium gallium zinc oxide (InGaZnO) thin film transistor hot carrier effect, the etching terminating layer contact window type element because of source pole and drain pole excess electrode leads to electron injection in drain pole excess electricity and lower channel etch stop layer, and the injected electron will be confined to the excess electrode position, such electronic injection state gate source capacitance curves is due to the phenomenon of two-stage uplift. The relationship between the thermal field emission activation energy and the work function of the metal materials can be found by the amount of different electrode materials.

Contents
論文審定書 i
誌謝 ii
摘要 iv
Abstract vi
Contents x
Figure Captions xiii
Chapter 1 Introduction 1
1.1 General Background of Thin-Film Transistor (TFT) 1
1.2 Overview of Amorphous Oxide Semiconductors 2
1.3 Overviews of Active-Matrix Flat Panel Displays 3
1.4 Motivation 5

Chapter 2 Fabrication and Characterization 11
2.1 Fabrication Process Flow of Amorphous InGaZnO 11
2.1.1 Inverted coplanar structure a-InGaZnO TFTs 11
2.1.2 Etching-stop-layer structure with via-contact type a-InGaZnO TFTs 11
2.2 Methods of Device Parameter Extraction. 12
2.2.1 The threshold voltage extraction method 12
2.2.2 The carrier mobility extraction method 13
2.2.3 The subthreshold swing extraction method 13
2.3 Instability of Amorphous InGaZnO Thin Film Transistors 14
2.3.1 Instability of Electrical Bias Operation 14
2.3.2 Instability in Different Environments 16
2.3.3 Instability under Light Illumination 17

Chapter 3 Reduction of Defect Formation in Amorphous InGaZnO Thin Film Transistor by N2O Plasma Treatment 28
3.1 Introduction 28
3.2 Experiment 29
3.3 Results and Discussion 30
3.4 Summary 33

Chapter 4 Investigation of Hydration Reaction induced Protons Transport in Etching-Stop Amorphous InGaZnO Thin-Film Transistors 39
4.1 Introduction 39
4.2 Experiment 40
4.3 Results and Discussion 41
4.4 Summary 44

Chapter 5 Negative Bias Illuminate Stress-induced hole-trapping in Amorphous InGaZnO TFTs with Various Drain Voltage Bias 55
5.1 Introduction 55
5.2 Experiment 56
5.3 Results and Discussion 57
5.4 Summary 59

Chapter 6 Investigating Degradation Behaviors Induced by Hot-Carriers in the ESL in Amorphous InGaZnO TFTs with different Electrode materials and structure 67
6.1 Introduction 67
6.2 Experiment 68
6.3 Results and Discussion 69
6.3.1 Hot-carrier stress with different electrode materials 70
6.3.2 Hot-carrier stress with different electrode structures 70
6.4 Summary 72

Chapter 7 Conclusion 79

Chapter 1
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Chapter 5
1. P. Gorrn, M. Lehnhardt, T. Riedl, and W. Kowalsky, "The influence of visible light on transparent zinc tin oxide thin film transistors," Applied Physics Letters, vol. 91, pp. 193504-193504-3, 2007.
2. T.-C. Chen, T.-C. Chang, T.-Y. Hsieh, C.-T. Tsai, S.-C. Chen, C.-S. Lin, M.-C. Hung, C.-H. Tu, J.-J. Chang, and P.-L. Chen, "Light-induced instability of an InGaZnO thin film transistor with and without SiO passivation layer formed by plasma-enhanced-chemical-vapor-deposition," Applied Physics Letters, vol. 97, p. 192103, 2010.
3. P.-T. Liu, Y.-T. Chou, and L.-F. Teng, "Environment-dependent metastability of passivation-free indium zinc oxide thin film transistor after gate bias stress," Applied Physics Letters, vol. 95, pp. 233504-233504-3, 2009.
4. W.-F. Chung, T.-C. Chang, H.-W. Li, S.-C. Chen, Y.-C. Chen, T.-Y. Tseng, and Y.-H. Tai, "Environment-dependent thermal instability of sol-gel derived amorphous indium-gallium-zinc-oxide thin film transistors," Applied Physics Letters, vol. 98, pp. 152109-152109-3, 2011.
5. J.-H. Shin, J.-S. Lee, C.-S. Hwang, S.-H. K. Park, W.-S. Cheong, M. Ryu, C.-W. Byun, J.-I. Lee, and H. Y. Chu, "Light effects on the bias stability of transparent ZnO thin film transistors," ETRI Journal, vol. 31, pp. 62-64, 2009.
6. F. Libsch and J. Kanicki, "Bias‐ stress‐ induced stretched‐ exponential time dependence of charge injection and trapping in amorphous thin‐film transistors," Applied Physics Letters, vol. 62, pp. 1286-1288, 1993.
7. K. Takechi, M. Nakata, T. Eguchi, H. Yamaguchi, and S. Kaneko, "Comparison of ultraviolet photo-field effects between hydrogenated amorphous silicon and amorphous InGaZnO4 thin-film transistors," Japanese Journal of Applied Physics, vol. 48, p. 0203, 2009.
8. T.-C. Chen, T.-C. Chang, C.-T. Tsai, T.-Y. Hsieh, S.-C. Chen, C.-S. Lin, M.-C. Hung, C.-H. Tu, J.-J. Chang, and P.-L. Chen, "Behaviors of InGaZnO thin film transistor under illuminated positive gate-bias stress," Applied Physics Letters, vol. 97, pp. 112104-112104-3, 2010.
9. T.-C. Chen, T.-C. Chang, T.-Y. Hsieh, W.-S. Lu, F.-Y. Jian, C.-T. Tsai, S.-Y. Huang, and C.-S. Lin, "Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor," Applied Physics Letters, vol. 99, pp. 022104-022104-3, 2011.

Chapter 6
1. K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors," Nature, vol. 432, pp. 488-492, 2004.
2. E. M. Fortunato, P. M. Barquinha, A. Pimentel, A. M. Gonçalves, A. J. Marques, L. M. Pereira, and R. F. Martins, "Fully Transparent ZnO Thin‐Film Transistor Produced at Room Temperature," Advanced Materials, vol. 17, pp. 590-594, 2005.
3. H. Yabuta, M. Sano, K. Abe, T. Aiba, T. Den, H. Kumomi, K. Nomura, T. Kamiya, and H. Hosono, "High-mobility thin-film transistor with amorphous InGaZnO4 channel fabricated by room temperature rf-magnetron sputtering," Applied Physics Letters, vol. 89, pp. 112123-112123-3, 2006.
4. H. Lim, H. Yin, J.-S. Park, I. Song, C. Kim, J. Park, S. Kim, S.-W. Kim, C. B. Lee, and Y. C. Kim, "Double gate GaInZnO thin film transistors," Applied Physics Letters, vol. 93, pp. 063505-063505-3, 2008.
5. K.-S. Son, J.-S. Jung, K.-H. Lee, T.-S. Kim, J.-S. Park, Y.-H. Choi, K. Park, J.-Y. Kwon, B. Koo, and S.-Y. Lee, "Characteristics of double-gate Ga–In–Zn–O thin-film transistor," Electron Device Letters, IEEE, vol. 31, pp. 219-221, 2010.
6. H.-W. Zan, W.-T. Chen, C.-C. Yeh, H.-W. Hsueh, C.-C. Tsai, and H.-F. Meng, "Dual gate indium-gallium-zinc-oxide thin film transistor with an unisolated floating metal gate for threshold voltage modulation and mobility enhancement," Applied Physics Letters, vol. 98, pp. 153506-153506-3, 2011.
7. I.-T. Cho, J.-M. Lee, J.-H. Lee, and H.-I. Kwon, "Charge trapping and detrapping characteristics in amorphous InGaZnO TFTs under static and dynamic stresses," Semiconductor Science and Technology, vol. 24, p. 015013, 2009.
8. T.-C. Chen, T.-C. Chang, T.-Y. Hsieh, W.-S. Lu, F.-Y. Jian, C.-T. Tsai, S.-Y. Huang, and C.-S. Lin, "Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor," Applied Physics Letters, vol. 99, pp. 022104-022104-3, 2011.
9. J.-H. Shin, J.-S. Lee, C.-S. Hwang, S.-H. K. Park, W.-S. Cheong, M. Ryu, C.-W. Byun, J.-I. Lee, and H. Y. Chu, "Light effects on the bias stability of transparent ZnO thin film transistors," ETRI Journal, vol. 31, pp. 62-64, 2009.
10. F. Libsch and J. Kanicki, "Bias‐ stress‐ induced stretched‐ exponential time dependence of charge injection and trapping in amorphous thin‐film transistors," Applied Physics Letters, vol. 62, pp. 1286-1288, 1993.
11. T.-Y. Hsieh, T.-C. Chang, Y.-T. Chen, P.-Y. Liao, T.-C. Chen, M.-Y. Tsai, Y.-C. Chen, B.-W. Chen, A.-K. Chu, and C.-H. Chou, "Hot-Carrier Effect on Amorphous In-Ga-Zn-O Thin-Film Transistors With a Via-Contact Structure," IEEE Electron Device Letters, vol. 34, pp. 638-640, 2013.
12. T.-Y. Hsieh, T.-C. Chang, Y.-T. Chen, P.-Y. Liao, T.-C. Chen, M.-Y. Tsai, Y.-C. Chen, B.-W. Chen, A.-K. Chu, and C.-H. Chou, "Characterization and Investigation of a Hot-Carrier Effect in Via-Contact Type a-InGaZnO Thin-Film Transistors," IEEE Transactions on Electron Devices, vol. 60, pp. 1681-1688, 2013.