本論文針對無唯讀記憶體直接數位頻率合成器(ROM-less DDFS ) 之研究提出兩個主題，第一個主題是依均分式拋物線內插法設計之四階管線化無唯讀記憶體直接數位頻率合成器，使用TSMC 0.18 μm CMOS Mixed Signal/RF 製程，以驗証設計原理；第二個主題則是利用切換次數估算無唯讀記憶體直接數位頻率合成器之功率消耗，使在硬體化之前可以得知最低功耗之設計方式。

本論文第一個主題依均分式拋物線內插法設計之四階管線化無唯讀記憶體直接數位頻率合成器，係基於正弦波的對稱性，僅需先合成( 0 ~π/2)弧度正弦波，即可輸出一完整弦波。更重要的是考量到低硬體成本、高無雜訊動態範圍之下，分析不同的分段數，在不同的內插法方程式前提下，可得八段均分式二階拋物線內插法且採用四階管線化的架構為較佳的選擇。經量測驗証，最大無雜訊動態範
圍為74 dBc，且讓原本二階拋物線架構從參考時脈為50 MHz 提昇至71.9 MHz。

本論文第二個主題則針對硬體實現前，利用切換次數估算無唯讀記憶體直接數位頻率合成器之功率消耗。亦即在實現電路架構之前，就先利用切換次數估算出該架構的切換功率消耗，可以快速判斷出不同架構之間的功率消耗哪個較為節省功率。
本論文以線性內插法、拋物線內插法及類線性內插法等三種不同的直接數位頻率合成器之切換功率做比較，最大貢獻為針對其不同之內部子電路提出切換次數之公式，並以FPGA 驗証。

This thesis demonstrates two research topics for ROM-less DDFS (direct digital frequency synthesizer), including a 4-stage pipeline ROM-less DDFS design using equal division parabolic polynomial interpolation method, which is carried out by TSMC 0.18 μm CMOS Mixed Signal/RF process to justify the design theory and performance. Besides, a switching power estimation method for ROM-less DDFS designs using switching activity analysis is proposed.

The first topic shows a 4-stage pipeline ROM-less DDFS with equal division parabolic polynomial interpolation method which generates a complete sine wave based on the synthesis of a quarter of sine wave digital signal thanks to it symmetry characteristic. Considering the trade-off between the hardware cost and SFDR, different segments with various interpolation equations are analyzed. The equal 8-segment division with the 2nd-order parabolic equation turns out to be an optimal option. The maximum SFDR is measured to be 74 dBc on silicon. A 4-stage pipeline structure is then selected to elevate the clock rate up to 71.9 MHz.
A switching power estimation for DDFS designs using switching activity analysis is proposed in the second part of this thesis. A pre-realization switching power consumption approach for DDFS carries out the analysis of switching activity thereof. This method can quickly determine power consumption figure among different DDFS designs. Switching power consumptions with three DDFS architectures using linear interpolation, parabolic interpolation, and quasi−linear interpolation are compared by FPGA implementation to justify the correctness of the proposed method.

論文審定書. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
論文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1 概論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 相關文獻與研究探討. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 頻率合成器. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 直接數位頻率合成器. . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3 切換次數估算. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1 依均分式拋物線內插法設計之四階管線化無唯讀記憶體直接數位頻率合成器. . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.2 以切換次數估算無唯讀記憶體直接數位頻率合成器之功率消耗12
1.4 論文大綱. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 依均分式拋物線內插法設計之四階管線化無唯讀記憶體直接數位頻率合成器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 電路架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 ROM-less DDFS 電路設計. . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 四種拋物線方程式比較. . . . . . . . . . . . . . . . . . . . . . 15
2.3.2 相位累加器. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.3 相位振幅轉換器. . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.4 四階管線化直接數位頻率合成器. . . . . . . . . . . . . . . . 23
2.3.5 電源接墊數量計算. . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.6 晶片佈局圖. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4 電路模擬結果與預計規格. . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.1 電路模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5 FPGA 驗證結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.6 晶片量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.6.1 量測環境. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.2 晶片量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.7 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3 以切換次數估算無唯讀記憶體直接數位頻率合成器之功率消耗. . . . . . . 39
3.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 電路架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.1 加法器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.2 暫存器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.3 多工器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.4 移位器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2.5 乘法器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3 切換次數計算. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.1 利用拋物線內插法之DDFS 之切換次數計算. . . . . . . . . . 50
3.3.2 利用類線性內插法之DDFS 之切換次數計算. . . . . . . . . . 51
3.3.3 利用線性內插法之DDFS 之切換次數計算. . . . . . . . . . . 52
3.4 電路模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.5 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4 結論與未來研究方向. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.1 研究成果與結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 未來研究規劃. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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