在本篇論文中，我們提出了一新式垂直奈米柱架構(Vertical Pillar Structure)應用於雙閘極單電晶體動態隨機存取記憶體(Double Gate One Transistor Dynamic Random Access Memory, DG 1T-DRAM)製作在超薄主體層(Ultra-Thin Body)架構上。根據模擬結果，我們發現延展主體層(i.e. 垂直奈米柱)架構不僅能提供更大的電洞儲存區域以達到屈膝效應(Kink Effect)之外，更因為延展主體層和電子反轉層通道垂直，讓電洞不會立即復合而達到非常長的資料保存時間。可程式規劃窗(Programming Window, PW)雖因架構關係，使VPDG架構的表現較傳統架構小，但是延伸主體層讓VPDG架構的驅動電流表現較傳統架構大；資料保存時間(Data Retention Time, RT)於使用撞擊游離和閘極引致漏電流機制時，VPDG架構表現分別高達傳統架構的6.15 × 103倍和4.32 × 104倍。於高溫狀態下，傳統架構的PW操作於撞擊游離和閘極引致漏電流機制時，衰退分別高達54.7 %和61.08 %；而VPDG架構僅分別衰退46.38 %和17.75 %。微縮化表現上，VPDG架構不論於PW和RT皆優於傳統架構，顯現了VPDG架構亦符合未來微縮化的需求。我們提出的具自我對準和完全符合現今CMOS製程的垂直奈米柱雙閘極單電晶體動態隨機存取記憶體(VPDG 1T-DRAM)，擁有著資料保存時間非常長、溫度免疫性高、可微縮化和元件製作成陣列電路干擾低的優點。使得VPDG的DRAM元件成為未來一個取代傳統DRAM的極佳選擇。

In this paper, we propose a new vertical pillar structure for double gate (VPDG) 1T-DRAM with ultra-thin body. According to the results of simulation, we have found out that extended body region (i.e. Vertical Pillar) provides an additional region which can store more excess holes to achieve kink effect easily. Moreover, a longer retention time is obtained by the advantage of the extended body region which is perpendicular to the electron inversion channel, and makes the excess holes not be recombined immediately. Due to the vertical pillar structure, the programming window of VPDG structure is smaller than that of conventional structure. But that also makes VPDG structure have a higher drain current than conventional structure. Both of the impact ionization and gate-induced drain-leakage mechanisms we used, the data retention times of VPDG structure are 6.15 × 103 and 4.32 × 104 times bigger than those of conventional one, respectively. In addition, the performance of thermal immunity of VPDG structure is much better than conventional structure. At high temperature condition, the PW values of the conventional structure under I.I. and GIDL operation mechanisms are degraded 54.7 % and 61.08 %, respectively. Meanwhile, the PW degradation percentage of the VPDG structure under I.I. and GIDL operation mechanisms are 46.38 % and 17.75 %, respectively. As the device scales down, VPDG structure still shows better programming window and data retention time than conventional one. The fabrication process of VPDG structure is self-aligned and fully compatible with the CMOS technology. VPDG structure also has the advantages of longer data retention time, great thermal immunity, scalability and great disturb immunity. VPDG DRAM becomes one of best choice to replace conventional DRAM.

論文審定書.....................................................................................................................i
英文論文審定書............................................................................................................ii
致謝...............................................................................................................................iii
摘要...............................................................................................................................iv
Abstract..........................................................................................................................v
第一章 導論 1
1.1 研究背景 1
1.2 動機 11
第二章 操作原理 12
2.1 運用機制說明 12
2.2 元件操作說明 13
2.2.1 撞擊游離機制(Impact Ionization, I.I.) 13
2.2.2 閘極引致汲極漏電流機制(Gate-Induced Drain-Leakage, GIDL) 14
2.2.3 寄生雙極性電晶體讀取機制(Parasitic BJT Read Method) 14
第三章 元件製作 17
3.1 模擬元件 17
3.2 實作元件 19
第四章 研究方法與結果討論 20
4.1 物理機制模型 20
4.2 元件架構說明 22
4.3 元件基本電性 24
4.4 撞擊游離機制之元件記憶體特性 27
4.4.1 撞擊游離之可程式規劃窗 (Programming Window, PW) 29
4.4.2 撞擊游離之資料保存時間 (Data Retention Time, RT) 34
4.4.3 撞擊游離之溫度改變對元件記憶體特性的影響 38
4.4.4 撞擊游離之元件微縮化探討 41
4.4.5 撞擊游離之元件於電路陣列干擾探討 45
4.5 閘極引致汲極漏電流機制之元件記憶體特性 51
4.5.1 閘極引致汲極漏電流之可程式規劃窗 52
4.5.2 閘極引致汲極漏電流之資料保存時間 54
4.5.3 閘極引致汲極漏電流之溫度改變對元件記憶體特性之影響 55
4.6 邊際效應之比較 (Benchmark comparison) 59
4.7 寄生雙極性電晶體讀取機制研究與探討 61
4.8 實作結果與量測 66
第五章 結論與未來展望 70
5.1 結論 70
5.2 未來展望 71
參考文獻......................................................................................................................72
附錄..............................................................................................................................80
論文著述......................................................................................................................96
個人得獎......................................................................................................................97

[1] J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li, and C. J. Radens, “Challenges and future directions for the scaling of dynamic random-access memory (DRAM),” IBM J. Res. Develop., vol. 46, no. 2.3, pp. 187－212, Mar. 2002.
[2] A. Nitayama, Y. Kohyama, and K. Hieda, “Future Directions For DRAM Memory Cell Technology,” in IEDM Tech. Dig., Dec. 1998, pp. 355－358
[3] N. C.-C. Lu, P. E. Cottrell, W. J. Craig, S. Dash, D. L. Critchlow, R. L. Mohler, B. J. Machesney, T. H. Ning, W. P. Noble, R. M. Parent, R. E. Scheuerlein, E. J. Sprogis, and L. M. Terman, “A Substrate-Plate Trench-Capacitor ( SPT) Memory Cell for Dynamic RAM’s,” IEEE J. Solid-State Circuits, vol. 21, no. 5, pp. 627－634, Oct. 1986.
[4] T. Kaga, T. Kure, H. Shinriki, Y. Kawamoto, F. Murai, T. Nishida, Y. Nakagome, D. Hisamoto, T. Kisu, E. Takeda, and K. Itoh, “Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM’s,” IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 255－261, Feb. 1991.
[5] S. Cristoloveanu, “Silicon on insulator technologies and devices: from present to future,” Solid State Electron., vol. 45, no. 8, pp. 1403－1411, Aug. 2001.
[6] J. Tihanyi, and H. Schlötterer, “Properties of ESFI MOS Transistors Due to the Floating Substrate and the Finite Volume,” IEEE Trans. Electron Devices, vol. 22, no. 11, pp. 1017－1023, Nov. 1975.
[7] M. R. Tack, M. Gao, C. L. Claeys, and G. J. Declerck, “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures,” IEEE Trans. Electron Devices, vol. 37, no. 5, pp. 1373－1382, May 1990.
[8] H. J. Wann, and C. Hu, “A Capacitorless DRAM Cell on SOI Substrate,” in IEDM Tech. Dig., Dec. 1993, pp. 635－638.
[9] S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, “A SOI Capacitor-less 1T-DRAM Concept,” in Proc. IEEE Int. SOI Conf., Oct. 2001, pp.153－154.
[10] P. C. Fazan, S. Okhonin, M. Nagoga, and J. M. Sallese, “A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs,” in Proc. IEEE Custom Integr. Circuits Conf., 2002, pp. 99－102.
[11] J. T. Lin, K. D. Huang, and B. T. Jheng, “Performances of a Capacitorless 1T-DRAM Using Polycrystalline Silicon Thin-Film Transistors With Trenched Body,” IEEE Electron Device Lett., vol. 29, no. 11, pp. 1222－1225, Nov. 2008.
[12] J. H. Han, S. W. Ryu, D. H. Kim, C. J. Kim, S. Kim, D. I. Moon, S. J. Choi, and Y. K. Choi, “Fully Depleted Polysilicon TFTs for Capacitorless 1T-DRAM,” IEEE Electron Device Lett., vol. 30, no. 7, pp. 742－744, Jul. 2009.
[13] J. W. Han, C. J. Kim, S. J. Choi, D. H. Kim, D. I. Moon, and Y. K. Choi, “Gate-to-Source/Drain Nonoverlap Device for Soft-Program Immune Unified RAM (URAM),” IEEE Electron Device Lett., vol. 30, no. 5, pp. 544－546, May 2009.
[14] J. W. Han, S. W. Ryu, D. H. Kim, and Y. K. Choi, “Polysilicon Channel TFT With Separated Double-Gate for Unified RAM (URAM)—Unified Function for Nonvolatile SONOS Flash and High-Speed Capacitorless 1T-DRAM,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 601－607, Mar. 2010.
[15] J. K. Park, and W. J. Cho, “Dual Read Method by Capacitance Coupling Effect for Mode-Disturbance-Free Operation in Channel-Recessed Multifunctional Memory,” IEEE Electron Device Lett., vol. 33, no. 12, pp. 1708－1710, Dec. 2012.
[16] M. Lee, T. Moon, and S. Kim, “Floating Body Effect in Partially Depleted Silicon Nanowire Transistors and Potential Capacitor-Less One-Transistor DRAM Applications,” IEEE Trans. On Nanotechnology, vol. 11, no. 2, pp. 355－359, Mar. 2012.
[17] E. Yoshida, and T. Tanaka, “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory,” in IEDM Tech. Dig., Dec. 2003, pp. 37.6.1－37.6.4.
[18] E. Yoshida, and T. Tanaka, “A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 692－697, Apr. 2006.
[19] Z. Lu, J. G. Fossum, J.-W. Yang, H. R. Harris, V. P. Trivedi, M. Chu, and S. E. Thompson, “A Simplified Superior Floating-Body/Gate DRAM Cell,” IEEE Electron Device Lett., vol. 30, no. 3, pp. 282－284, Mar. 2009.
[20] G. Kim, S. W. Kim, J. Y. Song, J. P. Kim, K.-C. Ryoo, J.-H. Oh, J. H. Park, H. W. Kim, and B.-G. Park, “Body-Raised Double-Gate Structure for 1T DRAM,” in Nanotechnology Materials and Devices Conf., Jun. 2009, pp. 259－263.
[21] J.-W. Han, S.-W. Ryu, S.-J. Choi, and Y.-K. Choi, “Gate-Induced Drain-Leakage (GIDL) Programming Method for Soft-Programming-Free Operation in Unified RAM (URAM),” IEEE Electron Device Lett., vol. 30, no. 2, pp. 189－191, Feb. 2009.
[22] K.-H. Park, C. M. Park, S. H. Kong, and J.-H. Lee, “Novel Double-Gate 1T-DRAM Cell Using Nonvolatile Memory Functionality for High-Performance and Highly Scalable Embedded DRAMs,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 614－619, Mar. 2010.
[23] J.-W. Han, D.-I. Moon, D.-H. Kim and Y.-K. Choi, “Parasitic BJT Read Method for High-Performance Capacitorless 1T-DRAM Mode in Unified RAM,” IEEE Electron Device Lett., vol. 30, no. 10, pp.1108－1110, Oct. 2009.
[24] Z. Zhou, J. G. Fossum, and Z. Lu, “Physical Insights on BJT-Based 1T DRAM Cells,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 565－567, May 2009.
[25] S.-J. Choi, J.-W. Han, D.-I. Moon, and Y.-K. Choi, “Analysis and Evaluation of a BJT-Based 1T-DRAM,” IEEE Electron Device Lett., vol. 31, no. 5, pp. 393－395, May 2010.
[26] G. Giusi, M. A. Alam, F. Crupi, and S. Pierro, “Bipolar Mode Operation and Scalability of Double-Gate Capacitorless 1T-DRAM Cells,” IEEE Trans. Electron Devices, vol. 57, no. 8, pp. 1743－1750, Aug. 2010.
[27] D.-I. Moon, S.-J. Choi, J.-W. Han, S. Kim, and Y.-K. Choi, “Fin-Width Dependence of BJT-Based 1T-DRAM Implemented on FinFET,” IEEE Electron Device Lett., vol. 31, no. 8, pp. 909－911, Sep. 2010.
[28] D.-I. Moon, J.-Y. Kim, J.-B. Moon, D.-O. Kim, and Y.-K. Choi, “Evolution of Unified-RAM: 1T-DRAM and BE-SONOS Built on a Highly Scaled Vertical Channel,” IEEE Trans. Electron Devices, vol. 61, no. 1, pp. 60－65, Jan. 2014.
[29] T. Hamamoto, and T. Ohsawa, “Overview and Future Challenges of Floating Body RAM (FBRAM) Technology for 32nm Technology Node and Beyond,” in Proc. ESSDERC, Sep. 2008, pp. 25－29.
[30] A. Hubert, M. Bawedin, G. Guegam, S. Cristoloveanu, T. Ernst, and O. Faynot. “Experimental comparison of programming mechanisms in 1T-DRAM cells with variable channel length,” in Proc. ESSDERC, Sep. 2010, pp. 150－153.
[31] D.-I. Bae, S. Kim, and Y.-K. Choi, “Low-Cost and Highly Heat Controllable Capacitorless PiFET (Partially Insulated FET) 1T DRAM for Embedded Memory,” IEEE Trans. On Nanotechnology, vol. 8, no. 1, pp. 100－105, Jan. 2009.
[32] R. Ranica, A. Villaret, P. Malinge, P. Mazoyer, D. Lenoble, P. Candelier, F. Jacquet, P. Masson, R. Bouchakour, R. Fournel, J. P. Schoellkopf, and T. Skotnicki, “A One Transistor Cell on Bulk Substrate (1T-Bulk) for Low-Cost and High Density eDRAM,” in VLSI Symp. Tech. Dig., Jun. 2004, pp. 128－129.
[33] N. Collaert, M. Aoulaiche, B. D. Wachter, M. Rakowski, A. Redolfi, S. Brus, A. D. Keersgieter, N. Horiguchi, L. Altimime, and M. Jurczak, “A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C,” in VLSI Symp. Tech. Dig., Jun. 2010, pp. 161－162.
[34] M. G. Ertosun, P. Kapur, and K. C. Saraswat, “A Highly Scalable Capacitorless Double Gate Quantum Well Single Transistor DRAM: 1T-QW DRAM,” IEEE Electron Device Lett., vol. 29, no. 12, pp. 1405－1407, Dec. 2008.
[35] M. G. Ertosun, and K. C. Saraswat, “Investigation of Capacitorless Double-Gate Single-Transistor DRAM: With and Without Quantum Well,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 608－613, Mar. 2010.
[36] S. Lee, J. S. Shin, J. Jang, H. Bae, D. Yun, J. Lee, D. H. Kim, and D. M. Kim, “A Novel Capacitorless DRAM Cell Using Superlattice Bandgap-Engineered (SBE) Structure With 30-nm Channel Length,” IEEE Trans. On Nanotechnology, vol. 10, no. 5, pp. 1023－1030, Sep. 2011.
[37] K.-S. Shim, I.-Y. Chung, and Y. J. Park, “A BJT-Based Heterostructure 1T-DRAM for Low-Voltage Operation,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 14－16, Jan. 2012.
[38] J. S. Shin, H. Choi, H. Bae, J. Jang, D. Yun, E. Hong, D. H. Kim, and D. M. Kim, “Vertical-Gate Si/SiGe Double-HBT-Based Capacitorless 1T DRAM Cell for Extended Retention Time at Low Latch Voltage,” IEEE Electron Device Lett., vol. 33, no. 2, pp. 134－136, Feb. 2012.
[39] M. G. Ertosun, k.-Y. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat, “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electrons,” IEEE Electron Device Lett., vol. 31, no. 5, pp. 405－407, May 2010.
[40] D.-I. Moon, S.-J. Choi, J.-W. Han, and Y.-K. Choi, “An Optically Assisted Program Method for Capacitorless 1T-DRAM,” IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1714－1718, Jul. 2010.
[41] W. Lee, and W. Y. Choi, “A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement,” IEEE Trans. On Nanotechnology, vol. 10, no. 3, pp. 462－466, May 2011.
[42] N. Rodriguez, F. Gamiz, and S. Cristoloveanu, “A-RAM Memory Cell: Concept and Operation” IEEE Electron Device Lett., vol. 31, no. 9, pp. 972－974, Sep. 2010.
[43] N. Rodriguez, S. Cristoloveanu, and F. Gamiz, “Capacitor-less A-RAM SOI memory: Principles, scaling and expected performance,” Solid State Electronic, vol. 59, no. 1, pp. 44－49, May 2011.
[44] N. Rodriguez, S. Cristoloveanu, and F. Gamiz, “Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates,” IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2371－2377, Aug. 2011.
[45] N. Rodriguez, C. Navarro, F. Gamiz, F. Andrieu, O. Faynot, and S. Cristoloveanu, “Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator,” IEEE Electron Device Lett., vol. 33, no. 12, pp. 1717－1719, Dec. 2012.
[46] N. Rodriguez, F. Gamiz, C. Marquez, C. Navarro, F. Andrieu, O. Faynot, and S. Cristoloveanu, “Fabrication and Validation of A2RAM Memory Cells on SOI and Bulk Substrates,” in IEEE IMW, 2013, pp. 135－138.
[47] J. Tihanyi, and H. Schlötterer, “PROPERTIES OF ESFI MOS TRANSISTORS DUE TO THE FLOATING SUBSTRATE AND THE FINITE VOLUME,” in IEDM Tech. Dig., Dec. 1974, pp. 39－42.
[48] M. Matloubian, C.-E. D. Chen, B.-Y. Mao, R. Sundaresan, and G. P. Pollack, ”Modeling of the Subthreshold Characteristics of SOI MOSFET’s with Floating Body,” IEEE Trans. Electron Devices, vol. 37, no. 9, pp. 1985－1994, Sep. 1990.
[49] J.-Y. Choi, and J. G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1384－1391, Jun. 1991.
[50] T. Tanaka, E. Yoshida, and T. Miyashita, “Scalability Study on a Capacitorless 1T-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM,” in IEDM Tech. Dig., Dec. 2004, pp. 919－922.
[51] T. Hamamoto, Y. Minami, T. Shino, A. Sakamoto, T. Higashi, N. Kusunoki, K. Fujita, K. Hatsuda, T. Ohsawa, N. Aoki, H. Tanimoto, M. Morikado, H. Nakajima, K. Inoh, and A. Nitayama, “A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications,” in IEEE Int. Conf. ICDT, 2006, pp. 1－6.
[52] S. Puget, G. Bossu, C. F.-Beranger, P. Perreau, P. Masson, P. Mazoyer, P. Lorenzini, J.-M. Portal, R. Bouchakour, and T. Skotnicki, “FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications,” in IEEE IMW, May 2009, pp. 1－2.
[53] M. Aoulaiche, N. Collaert, R. Degraeve, Z. Lu, B. D. Wachter, G. Groeseneken, M. Jurczak, and L. Altimime, “BJT-Mode Endurance on a 1T-RAM Bulk FinFET Device,” IEEE Trans. Electron Devices, vol. 31, no. 12, pp. 1380－1382, Dec. 2010.
[54] Sentaurus User’s Manual, ver. H-2013.03, Synopsys, Inc.
[55] (2013). The International Technology Roadmap for Semiconductors (ITRS) [Online]. Available: http://public.itrs.net
[56] S. Okhonin, M. Nagoga, E. Carman, R. Beffa, E. Faraoni, “New Generation of Z-RAM,” in IEDM Tech. Dig., Dec. 2007, pp. 925－928.