近年來隨著顯示器產業的迅速發展，對於做為畫素開關元件以及電流驅動元件的薄膜電晶體之要求也隨之增加。以傳統的非晶矽薄膜電晶體而言其電子遷移率太低(< 1 cm2/Vs)，因此擁有高電子遷移率的低溫複晶矽薄膜電晶體以及非晶態金屬氧化物薄膜電晶體應用在未來的顯示器上是非常有潛力的。
本論文首先將探討低溫複晶矽薄膜電晶體應用於非揮發性記憶體SONOS(Silicon-Oxide-Nitride-Oxide-Silicon)元件在寫入與抹除下之穩定性與可靠度分析。結果顯示元件經過電子寫入操作後會有很明顯之缺陷輔助閘極引發汲極端&#63822;電(trap-assisted-gate-induced-drain-leakage)現象發生，主要由於注入在汲極端上方之電子提升了局部之電場導致漏電流增加，而此漏電流會造成寫入抹除之記憶體讀取窗口變小增加訊號誤判的機會。因此，為了抑制此漏電流現象，此論文提出了熱電洞(band-to-band hot-hole)注入之方式改善汲極端局部之垂直電場進而在不影響臨界電壓(Vt)下改善漏電流，此方法經實驗驗證在多次寫入抹除以及高溫操作下依然保有良好之漏電流抑制效果。另一方面，作為畫素開關元件，大部分時間元件都操作在非導通狀態(Off-state)，因此本論文進一步討論元件在非導通狀態操作下之可靠度問題。實驗結果顯示在初始記憶狀態(Fresh-state)下之非導通操作由於大量熱電洞注入會造成元件導通電流劣化，而同樣之非導通操作條件在不同記憶體狀態下會呈現不同之劣化趨勢，經由模擬軟體ISE TCAD的驗證可以得知此劣化趨勢之差異是由注入之熱電洞與缺陷之相對位置所造成。
本論文另一部分著重在非晶態銦鎵鋅金屬氧化物薄膜電晶體之穩定性與可靠度分析。首先探討元件在閘極電壓下之可靠度，在正閘極電壓操作下由於電子被捕獲在主動層與閘極絕緣層介面因此呈現明顯的次臨界電壓向右偏移。而在閘極負偏壓操作卻無明顯之劣化，其差異主要是由於銦鎵鋅金屬氧化物是n型半導體且由於其導帶上之大量缺陷分佈的原故不易產生電洞反轉現象，此外也因為電洞在主動層之載子移動率遠低於電子，因此不會產生電洞捕獲造成之臨界電壓劣化現象。另一方面在照光的環境下實施相同之正負閘極偏壓操作，實驗結果與暗態下呈現相反之劣化趨勢，在照光下產生大量之光激發電洞，而電洞獲得能量得以在閘極負偏壓下於主動層傳遞造成電洞捕獲之現象。由於能帶結構之差異造成在照光操作下電洞的捕獲遠比電子捕獲明顯。此外，為了探討元件在照光環境下穩定性，本論文利用有蓋二氧化矽保護層以及沒有蓋保護層之元件進行照光實驗。實驗結果顯示在無蓋保護層之元件其光不穩定性是由氧氣的吸附與脫附所造成之臨界電壓飄移所主導，而在蓋完保護層之元件則會因為在蓋保護層之過程中缺陷數目增加造成明顯之次臨界光漏電流。
接著，我們更進一步討論非晶態銦鎵鋅金屬氧化物薄膜電晶體在電性操作下的劣化機制。根據閘極偏壓以及汲極偏壓操作條件的不同，分別探討元件在熱載子(Hot-carrier stress)操作以及自我加熱(Self-heating stress)操作下之劣化機制。在熱載子操作下之元件除了因為電子捕獲所造成臨界電壓往右飄移外還有明顯的導通電流劣化現象，此劣化現象主要由在熱載子操作下產生之缺陷所造成，且由非對稱之電性可以了解缺陷的分佈是靠近汲極端。此外，利用非對稱源/汲極結構之元件，可以發現在相同熱載子操作下由於源/汲極電場分布不均的原故會造成很明顯的非對稱臨界電壓劣化現象。配合模擬軟體的驗證可以了解此現象是由通道熱載子注入(Channel Hot Electron Injection)在汲極端所造成。另一方面，當元件操作在自我加熱條件時，由於汲極電流會產生焦耳熱且在閘極正偏壓的條件下會產生介面缺陷。此外自我加熱效應更會加劇原本就有的電子捕獲現象，所以在相同的閘極偏壓下自我加熱操作所產生之臨界電壓飄移量會遠比閘極正電壓操作嚴重許多。
最後，我們探討雙閘極結構之非晶態銦鎵鋅金屬氧化物薄膜電晶體在不同閘極操作下之電性以及光敏感度之差異。實驗結果顯示不管是電性或是光敏感度在不同閘極操作下都呈現明顯的不對稱性。由模擬結果可以了解此非對稱的效應是由於上下閘極所控制之通道區域不同所造成。此外，藉由上下閘極操作下之光敏感度之差異可以應用於內嵌式(In Cell)觸控技術上，且相同觸控技術相較於傳統的非晶矽薄膜電晶體可以省去金屬遮罩層(Black Matrix)進而節省製程上的成本。

In order to meet the requests of the application as pixel switch and current driver in next generation active-matrix liquid crystal displays (AMLCD) and active-matrix organic light-emitting diodes (AMOLED). The materials of low temperature poly-silicon (LTPS) and metal-oxide are supposed to be the most potential material for active layer of thin-film transistors (TFTs) due to their high mobility compared to the traditional amorphous silicon TFTs. Therefore, in order to make the LTPS TFTs and metal-oxide TFTs affordable for the practical applications, the understanding of instability and reliability is critically important.
In the first part, we studied the nonvolatile memory characteristics of polycrystalline-silicon thin-film-transistors (poly-Si TFTs) with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant gate induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection method to counteract programmed electrons and this method can exhibit good sustainability because the injected hot holes can remain in the nitride layer after repeated operations. On the other hand, we also investigated the degradation behavior of SONOS-TFT under off-state stress. After the electrical stress, the significant on-state degradation indicates that the interface states accompanied with hot-hole injection. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Furthermore, we also performed the identical off-state stress for the device with different memory states. The different degradation behavior under different memory states is attributed to the different overlap region of injected holes and trap states.
In the second part, the degradation mechanism of indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs) caused by gate-bias stress performed in the dark and light illumination was investigated. The parallel threshold voltage indicates that charge trapping model dominates the degradation behavior under positive gate-bias stress. However, the degradation of negative gate bias stress is much slighter than the positive gate bias stress since the IGZO material is hard to induced hole inversion layer. In addition, the hole mobility is much lower than electron resulting in ignorable hole trapping effect. On the other hand, the identical positive and negative gate bias stress performed under light illumination exhibit opposite degradation behavior compared with dark stress. This degradation variation under dark and light illumination can be attributed to the effectively energy barrier variation of electron and hole trapping. Furthermore, to further investigate the light induced instability for IGZO TFTs, the device with and without a SiOx passivation were investigated under light illumination. The experiment results indicate that oxygen adsorption and desorption dominate the light induced instability for unpassivated device and the trap states caused during the passivation layer deposition process will induce apparent subthreshold photo-leakage current under light illumination.
In the third part, we investigated the degradation mechanism of IGZO TFTs under hot-carrier and self-heating stress. Under hot-carrier stress, except the electron trapping induced positive Vt shift, an apparent on-current degradation behavior indicates that trap states creation. On the other hand, the identical hot-carrier stress performed in the asymmetric source/drain structure exhibits different degradation behavior compared with symmetric source/drain structure. For asymmetric structure, the strong electrical field in the I-shaped drain electrode will induce channel hot electron injection near the drain side and cause asymmetric threshold voltage degradation. In this part we also investigated the degradation behavior under self-heating stress. The apparent positive threshold voltage (Vt) shift and on-current degradation indicate that the combination of trap states generation and electron trapping effect occur during stress. The trap states generation is caused by the combination of Joule heating and the large vertical field. Moreover, the Joule heating generated by self-heating operation can enhance electron trapping effect and cause larger Vt shift in comparison with the gate-bias stress.
Finally, the electrical properties and photo sensitivity of dual gate IGZO TFTs were investigated. The asymmetric electrical properties and photo sensitivity under top gate and bottom gate operation is attributed to the variation of gate control region. Furthermore, the obvious asymmetric photo sensitivity can be utilized to the In-cell touch panel technology and lower the process cost compared with the traditional a-Si TFTs due to the elimination of black matrix.

Contents
摘要 i
Abstract iv
Acknowledgements viii
Contents ix
Figure & Table Captions xi
Chapter 1 Introduction 1
1.1: Overview of Thin-Film Transistor (TFT) 1
1.2: Overview of Nonvolatile Memory Device 2
1.3: Amorphous Metal Oxide Semiconductor Thin Film Transistors (AOS TFTs) 3
1.4: Motivation 5
1.5: Organization of the Dissertation 6
References: 9
Chapter 2 Fabrication and Characterization 15
2.1: Fabrication Process Flow of LTPS SONOS TFT and a-IGZO TFT 15
2.1.1: Fabrication Process Flow of LTPS SONOS TFT 15
2.1.2: Fabrication Process Flow of a-IGZO TFTs 15
2.2: Methods of Device Parameter Extraction 16
2.2.1: Determination of the Threshold Voltage 16
2.2.2: Determination of the Field-Effect Mobility 16
2.3: The Electrical Characteristics of SONOS-Type Nonvolatile Memory 17
2.3.1: Operation of SONOS-Type Nonvolatile Memory 17
2.3.2: Programming Operation 18
2.3.3: Erasing Operation 20
2.4: Instability of Amorphous Oxide Semiconductor Thin Film Transistors 21
2.4.1: Instability under Electrical Bias Operation 21
2.4.2: Instability in Different Environments 23
2.4.3: Instability under Light Illumination 25
References: 28
Chapter 3 Electrical degradation of SONOS TFT for memory device and pixel switch operation 45
3.1: Introduction: 45
3.2: Experiment: 46
3.3: Results and Discussions: 47
3.3.1: Improvement of memory state misidentification caused by Gate Induced Drain Leakage current 47
3.3.2: Investigation of the degradation behavior caused by hot-hole injection for SONOS TFT 50
3.4: Conclusion: 54
Reference: 56
Chapter 4 Investigating the reliability and instability under light illumination for a-IGZO TFT 73
4.1: Introduction: 73
4.2: Experiment: 75
4.3: Results and Discussions: 75
4.3.1: Analyzing the degradation behavior of a-IGZO TFT under illuminated gate bias stress 75
4.3.2: Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor 80
4.3.3: Investigating the light induced instability for a-IGZO TFT with different device structure 82
4.4: Conclusion: 85
Reference: 87
Chapter 5 Degradation mechanism for a-IGZO TFT under electrical stress 106
5.1: Introduction: 106
5.2: Experiment: 107
5.3: Results and Discussions: 108
5.3.1: Investigating the hot-carrier degradation mechanism for a-IGZO TFT with symmetric and asymmetric structure 108
5.3.2: Self-Heating enhanced charge trapping effect for a-IGZO TFT 112
5.4: Conclusion: 115
References: 117
Chapter 6 Asymmetric electrical properties of Dual-Gate a-IGZO TFT and the application in touch panel 132
6.1: Introduction: 132
6.2: Experiment: 133
6.3: Results and Discussions: 134
6.3.1: Asymmetric electrical properties of Dual-Gate a-IGZO TFT under bottom gate control and top gate control 134
6.3.2: Asymmetric photo sensitivity of Dual-Gate a-IGZO TFT under bottom gate control and top gate control for the touch panel application 138
6.4: Conclusion: 140
References: 142
Chapter 7 Conclusion and Future Work 156
7.1: Conclusion: 156
7.2: Future Work: 158
Publication list 161

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