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博碩士論文 etd-0703105-201825 詳細資訊
Title page for etd-0703105-201825
論文名稱
Title
高速數位系統中靜電放電保護元件之研究
Investigation of ESD Protection Devices in High-speed Digital System
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
89
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2005-06-27
繳交日期
Date of Submission
2005-07-03
關鍵字
Keywords
電磁干擾、靜電放電、電磁相容、保護元件、浮接和接地系統
EMC, ESD, Floating and grounding system, EMI, Protection Device
統計
Statistics
本論文已被瀏覽 5970 次,被下載 12248
The thesis/dissertation has been browsed 5970 times, has been downloaded 12248 times.
中文摘要
現今電子產品趨向於運算速度快、省電、體積小、重量輕、可攜式之需求,高速數位系統之雜訊容忍度也相對的減小,然而在人造合成材料之大量生產下,人體愈來愈容易因摩擦而帶電,使得靜電放電問題對於電子產品之影響愈加嚴重。對於產品設計者而言,準確分析浮接與接地系統下之靜電放電現象,是目前相當重要之課題。
本論文提供靜電放電實驗之量測技巧,藉此提高量測之準確性與重複率。進而對於接地與浮接系統之靜電放電現象與靜電保護元件分別作詳細之研究探討,並對靜電保護元件建立一組等效SPICE模型,以提供在模擬分析上的驗證。
Abstract
In the trends of high clock rate, lower voltage, small volume, and portable requirement for present electric products, the noise immunity of high speed digital circuit becomes a critical factor for system designer. ESD problem becomes more and more important for electric products because of the triboelectricity caused by human body and synthetic material. It’s an important issue for designer to understand the ESD phenomena in grounding and floating system accurately.
In this thesis, a reliable setup for the ESD measurement is proposed both in grounding and floating systems. ESD behavior and protection devices are studied in detail and a corresponding SPICE model is built up for simulation validation.
目次 Table of Contents
論文提要 ii
目錄 iii
圖列 iv 
表列 x
第一章 序 1
1.1 動機與目的 1
1.2 論文大綱 1
第二章 靜電放電之簡介與規範 3
2.1 靜電放電簡介 3
2.1.1 靜電歷史 3
2.1.2 基本觀念 3
2.2 靜電放電之測試規範 8
2.2.1 靜電放電模型與規範簡介 8
2.2.2 IEC 61000-4-2 靜電槍簡單模型 8
2.2.3 靜電槍放電波形之驗證 10
2.2.4 靜電放電測試方法 11
第三章 靜電放電實驗之量測與設置 16
3.1 實驗設置與電磁干擾之討論 16
3.2 接地系統之影響 18
3.2.1 比較不同數位示波器 18
3.2.2 良好接地系統下量測仍然有靜電放電電磁輻射之干擾 19
3.3 靜電放電之電磁輻射 20
3.3.1 放變動距離之影響 20
3.3.2 探討電磁輻射源之耦合路徑 23
3.3.3 探討電磁輻射源之場強 24
3.3.4 在電波暗室屏蔽下量測仍然有共模電流之干擾 25
3.4 靜電放電之共模電流 26
3.4.1 探討共模電流之耦合路徑 27
3.4.2 探討共模電流之傳播方式 28
3.4.3 電波暗室之作用 29
3.4.4 磁性扼流線圈之影響 30
3.5 理想靜電放電實驗之設置 31
3.6 討論 32
第四章 接地系統中靜電放電保護元件之研究 33
4.1 靜電放電保護元件之介紹 33
4.1.1 陶瓷電容 33
4.1.2 積層式變阻器(MLV) 34
4.1.3 齊納二極體(zener diode) 35
4.1.4 暫態電壓抑制二極體(TVS diode) 35
4.2 靜電放電保護元件之量測 37
4.2.1 陶瓷電容 37
4.2.2 積層式變阻器 39
4.2.3 暫態電壓抑制二極體 40
4.2.4 積層式變阻器與電容的比較 40
4.3 積層式變阻器之模型與模擬 42
4.3.1 積層式變阻器之模型 42
4.3.2 電壓-電流曲線與趨勢線 43
4.3.3 ADS模擬設置 45
4.3.4 HSPICE之使用與模擬 45
4.4 討論 50
第五章 浮接系統中靜電放電保護元件之研究 51
5.1 浮接系統靜電放電主要放電路徑之低頻成份模型 51
5.1.1 CR-RC放電模型 51
5.2.2 CR-CC放電模型 53
5.2 浮接系統中靜電放電保護元件之量測 55
5.3 浮接系統靜電放電保護元件之模擬 62
5.4 討論 65
第六章 接地與浮接系統中靜電放電之比較 66
6.1 靜電放電雜訊源之比較 66
6.2 靜電放電保護元件¬:積層式變阻器與電容之比較 68
6.2.1 靜電放電保護元件對靜電放電雜訊源之抑制效果 68
6.2.2 靜電放電保護元件對訊號完整的影響 72
6.3 討論 74
第七章 結論與未來方向 75
6.1 結論 75
6.2 未來方向 75
參考文獻 76
參考文獻 References
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