這篇論文將著重於分析及探討同步切換雜訊在封裝和印刷電路板間的耦合行為，並提出一些有效抑制同步切換雜訊之設計。在此提出了二維時域有限差分法結合封裝與印刷電路板間集總電路模型的數值演算方法。藉由此演算法我們可以有效率地分析同步切換雜訊在封裝與印刷電路板間的耦合機制。此外在本篇論文中針對封裝及印刷電路板提出了電磁能隙電源供應層的設計概念，有效地抑制同步切換雜訊。此結構在電源供應層所夾的基板中，週期性地埋入高介電常數的材料。由模擬與量測中可發現這種電磁能隙結構不僅對於同步切換雜訊有寬頻的抑制效果同時也可降低所衍生出來的電磁輻射問題。

This thesis focuses on the modeling and solutions of the simultaneous switching noise (SSN) problems in the power delivery networks (PDN) of high-speed digital circuit packages. An efficient numerical approach based on two-dimension (2D) finite-difference time-domain (FDTD) method combined with the lumped circuit model of the interconnection is proposed to model the PDN of a package and PCB. Based on this approach, the mechanism of noise coupling between package and PCB can be analyzed. In addition, a novel photonic crystal power layer (PCPL) design for the PDN of the package or PCB is proposed to suppress the SSN. The periodic High-Dk material is embedded into the substrate layer between the power and ground planes. Both modeling and measurement demonstrate the PCPL can form a wide stopband well with excellent suppression of the SSN propagation in the substrate and the corresponding electromagnetic interference (EMI).

Abstract i
Contents iii
List of Figures v
Acronyms ix

1. Introduction 1
1.1 Research Motivations 1
1.2 Simultaneous Switching Noise (SSN) in the Power distributed Network (PDN) of the IC Package 1
1.3 Literature Survey and Contributions 3
1.4 Chapter Outline 6
2. 2D-FDTD Method for Modeling the Combined PDN 7
2.1 Maxwell’s Equation and Yee Algorithm 7
2.2 Numerical Stability 11
2.3 Lumped Circuit Elements and Resistive Voltage Source 11
2.4 Power Delivery Networks Modeling by 2D-FDTD Method 12
2.5 Theory of 2D-FDTD modeling linked with lumped network of interconnections 15
3. Modeling of PDN of a Package and PCB 22
3.1 Configurations of the test fixture and measurement 25
3.2 Equivalent circuit model for the combined PDN 28
3.3 SSN Coupling Between Package and PCB 32
3.4 Effect of SMT Capacitors on the Power Noise for the Combined Structure 42
3.4.1 Influence of Capacitor Position 43
3.4.2 Influence of Capacitor Value 44
3.4.3 Influence of Capacitor Number 45
3.5 Summary 47
4. Photonic Crystal Power/Ground Layer (PCPL) 49
4.1 PCPL Model and Design by 2D-FDTD Method 50
4.1.1 Photonic Crystal Power Layer Concept 51
4.1.2 PCPL Design and Fabrication 52
4.1.3 Bandgap Modeling by 2-D FDTD Method 53
4.2 Power Integrity Performance 57
4.2.1 Frequency Domain 57
4.2.2 Time Domain 60
4.3 Signal Integrity Performance 62
4.4 Radiated Emission 65
4.5 Design Diagram 68
5. Conclusion 73
Bibliography 75
Biography 82
Publication List 83

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