隨著科技的進步，功能整合及運算效能的要求越來越高，產品也朝著移動式及短小輕薄的方向發展，因此電池的電量就成為設計產品時的重要考量之一。而在繪圖影像方面，使用者也逐漸趨向於追求真實度，這使得處理圖形時，需要更大量的計算。因此加速資料的計算成為解決問題的方法之一，但伴隨而來的就是所消耗的功率也會跟著增大，因此產品的開發開始注重低功耗的設計。
本論文實作一個具有可變精確度運算模式之多執行緒統一圖形處理單元，主要使用ATTILA模擬器來協助開發，除了將傳統的頂點處理器及像素處理器結合之外，多執行緒則提供了八個執行緒來提升資料的生產量及使用率。為了減少功率消耗，調整了輸入的精確度，將向量運算單元及特殊函數運算單元都設計為四種精確度模式，並在算數處理單元做了低功耗的設計。此外，加入特殊的電路設計來減少資料切換，進而達到省電的效果。本論文使用clock gating的方式減少了clock power的消耗，以及其後所連接硬體的切換動作都跟著減少了。最終輸出的資料所呈現的影像誤差以人眼可以接受的程度為目標。

Following by the progressive technologies, the most important thing that people need to care about is power consumption due to the products toward portable and lightweight devices. Every day, people use electronic products and cannot separate their life without them. For the image processing appilcations on electronic products, human gradually pay attention to the image quality. In other words, it has to perform more computations. Therefore, improving the computation speed of electronic product becomes one way to solve this problem. However, higher computation ability will consume more power. Hence the designers begins to focus on low-power design.
In this thesis, we present a unified shader which combines variable precision modes and multi-thread based on ATTILA simulator. This shader combines vertex shader and pixel shader into one unified shader, and provides eight shaders to upgrade the throughput and the utility rate of data. Moreover, we integrate four precision modes into the vector arithmetic unit and the special function arithmetic unit to reduce the power consumption by adjusting the precision of the input and output operands. In addition, clock gating technique is applied to reduce the clock power of register files and pipeline registers, and the switching activities of these following hardware circuits. Following those steps, significant power saving can be achieved in the proposed multi-precision unified shader under the acceptable image distortion.

目錄
論文審定書 i
論文提要 ii
誌謝 iii
摘要 iv
Abstract v
目錄 vi
圖目錄 viii
表目錄 xi
第一章 緒論 1
1.1 研究動機 1
1.2 論文大綱 2
第二章 研究背景 3
2.1 三維繪圖簡介 3
2.1.1 三維繪圖管線流程（3D Rendering Pipeline） 3
2.1.2 座標轉換（Transformation Matrix） 5
2.1.3 Lighting 6
2.2 OpenGL ES簡介 7
2.3 ATTILA 3D繪圖模擬器 10
第三章 提出的統一著色器架構說明與設計 14
3.1 整體架構概要 15
3.2 Register files 16
3.3 指令集 18
3.3.1 指令格式 18
3.3.2 指令種類 23
3.3.3 Banks 24
3.4 管線各階段工作與硬體架構 25
3.4.1 指令擷取階段(instruction fetch) 26
3.4.2 執行緒單元架構 27
3.4.3 指令解碼階段(instruction decode) 28
3.4.4 Negative/Swizzle架構 29
3.4.5 Forwarding detection policy 30
3.4.6 Forwarding 架構 30
3.4.7 暫存器寫回階段(write back) 31
3.4.8 執行緒控制模組 32
3.4.9 執行緒狀態記錄表(thread_info) 33
3.4.10 RAW detection 34
3.5 運算單元 35
3.5.1 DP4 Architecture 36
3.5.2 Special Function Unit Architecture 38
3.6 Register file gating 39
3.7 Texture Unit 41
第四章 實驗結果 43
4.1 實驗方法與步驟 43
4.2 實驗數據 43
第五章 結論與未來研究方向 58
5.1結論 58
5.2未來研究方向 58
參考文獻 59

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[4] Khronos Group: http://www.khronos.org/
[5] ATTILA: http://attila.ac.upc.edu/wiki/index.php/Main_Page
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http://oss.sgi.com/projects/ogl-sample/registry/ARB/vertex_program.txt
[8] ARB Fragment Program Extension:
http://oss.sgi.com/projects/ogl-sample/registry/ARB/fragment_program.txt
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