在金氧半光伏元件的發展上，許多團隊將目標著重在光伏元件的效率提升，但單一光伏元件的開路電壓值無法滿足一般積體電路元件之驅動需求，又因共地問題而無法在單一晶片進行高壓串接多顆晶片，為此本論文使用被動式整合元件(integrated passive device, IPD)作為平台，並與實驗中所設計之積體化背面接觸式光伏元件進行封裝整合，以提升元件之開路電壓。整體光伏元件模組皆採用標準互補式金氧半CMOS製程進行製作，因此該升壓模組得以直接與其他積體電路整合，且此一設計亦不需更動目前所用之標準CMOS製程參數，在學術研究及實際應用之間能有良好的銜接。為達成此一升壓目的，我們在同一晶片上設計製作數顆子光伏元件，而後使用微機電後製程製作隔離溝槽，並利用元件基板薄化技術將子元件之相連基板部分除去，使彼此元件間得以電性獨立，解決寄生二極體及元件共地問題。我們接著使用覆晶黏著機將元件以低溫超音波震盪接合方式作金對金的黏合，大幅降低其走線電阻，並使元件以整合平台之佈局線路進行走線串接，最終達成元件升壓，使其開路電壓由原本的0.55V提升到2.04V，緊接著我們對元件之矽基板進行金屬誘發蝕刻以製作出抗反射奈米線結構，以降低表面反射率，使其整體效率得以由6.03%提升8.88%。而後便嘗試以此模組之電壓或電流驅動元件證明此可行性，考量到光伏元件於溫度變化下的特性改變，我們與台灣科技大學電子工程系陳伯奇教授合作，設計一可承受1.4V~2.2V之溫度感測電路，同時亦量測升壓模組的特性曲線確認其開路電壓的浮動值處在溫感電路之工作範圍內，量測結果發現在光伏元件或一般電壓源驅動之溫感輸出電壓皆與溫度成一線性關係，表示使用光伏元件是可行的。此外，我們亦成功利用光伏元件驅動垂直共振腔面射型雷射，相信未來此高壓輸出光伏元件可應用於遠端生醫供電或電磁場量測等。

The open-circuit voltage of a silicon-based photovoltaic device (PV) is typically 0.5V, which is not high enough to drive transistors fabricated by standard bulk complementary metal-oxide-semiconductor (CMOS) process. In this dissertation, we succeed in boosting the output voltage of a CMOS PV through the implementation of post-fabrication localized substrate removal (LSR). A metal-assisted chemical etching process is also conducted to produce an antireflective silicon surface. The resulting four-cell-cascaded CMOS PV module provides open-circuit voltage of 2.05-V, short-circuit current of 2.6-mA, electrical output power of 4.41-mW, and conversion efficiency of 11% under input laser intensity of 40-mW. The proposed LSR approach could be used in the stacking of on-chip PV cells to attain even higher voltages without the need for additional processing steps and without compromising device performance. The fact that the fabrication procedure of the proposed CMOS PV module is compatible with standard electronics manufacturing and packaging processes means that it is easily integrated with other microelectronics for the fabrication of self-powered systems. Finally, we also succeed in demonstrate that a CMOS temperature sensor and a vertical-cavity surface-emitting laser can be directly driven by the proposed CMOS PV module, indicating the feasibility of this approach for practical utilization.

[中文審定書+i]
[英文審定書+ii]
[致謝+iii]
[摘要+iv]
[Abstract+iv]
[內容目錄+v]
[圖目錄+ix]
[表目錄+xiii]
[第一章 緒論+1]
[1.1 前言+1]
[1.2 研究動機+2]
[1.3 文獻回顧+7]
[1.4 論文架構+13]
[第二章 光伏元件特性簡介+14]
[2.1光伏元件原理+14]
[2.2 光伏元件之電性參數介紹+16]
[2.2.1 開路電壓(Open Circuit Voltage, VOC)+17]
[2.2.2 短路電流(Short Circuit Current, ISC)+18]
[2.2.3 填充因子(Fill Factor, FF)+18]
[2.2.4 轉換效率(Conversion Efficiency, η)+18]
[2.3 影響轉換效率之因素+19]
[2.3.1受光面的反射損失(Reflection loss)+19]
[2.3.2載子複合損失(Recombination loss)+19]
[2.3.3電阻效應(Resistive effect)+19]
[2.3.4元件之環境溫度+21]
[2.3.5共地效應(Common ground issues)+22]
[2.4 奈米結構成長之技術原理與應用+23]
[第三章 下線晶片與製程簡介+27]
[3.1 實驗儀器介紹+27]
[3.1.1覆晶黏著機(Flip-Chip Bonder)+27]
[3.1.2電子束蒸鍍機(E-Gun)+29]
[3.1.3 掃描式電子顯微鏡(SEM)+30]
[3.2以標準CMOS製程架構設計之光伏元件簡介+32]
[3.2.1製程介紹及限制+32]
[3.2.2 MEMS後製程介紹+34]
[3.2.3下線晶片介紹+37]
[3.2.3.1第一代高壓輸出CMOS光伏元件模組+37]
[3.2.3.2第二代高壓輸出CMOS光伏元件模組+39]
[3.2.3.3第三代高壓輸出CMOS光伏元件模組+41]
[3.3 元件基板研磨製程+44]
[3.3.1基板局部去除製程(LSR)+46]
[3.4 元件封裝製程+47]
[3.5 抗反射結構製程+49]
[3.5.1 元件前處理流程+49]
[3.5.2 催化劑金薄膜沉積+50]
[3.5.3 矽奈米線蝕刻+50]
[第四章 量測結果分析及討論+52]
[4.1 量測系統架構+52]
[4.1.1 光場平坦化架構+53]
[4.2 光伏元件升壓數據分析+56]
[4.2.1第一代高壓輸出CMOS光伏元件模組+56]
[4.2.2第二代高壓輸出CMOS光伏元件模組+58]
[4.2.3第三代高壓輸出CMOS光伏元件模組+60]
[4.2.4 小結+62]
[4.3 矽奈米線後製程量測結果分析+63]
[4.4 溫度感測電路驅動+66]
[4.4.1 溫度感測電路設計架構+66]
[4.4.2 光伏元件於不同溫度下之特性變化+68]
[4.4.3 驅動結果比較+69]
[4.5 VCSEL雷射驅動結果分析+71]
[第五章 結論+74]
[5.1 成果與討論+74]
[5.2 未來改善方向+75]
[參考文獻+77]
[附錄+82]

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