本論文的第一個題目介紹一個全數位元件之低功率鎖相迴路電路。由於採用使用標準元件庫之設計方式，不但有效縮短設計時間，亦同時提高電路之可攜性與重覆使用性。針對全數位式鎖相迴路之功率消耗大，違反時序，與發生突波之問題，本設計提出一降低功率控制電路與多工器來解決。此全數位鎖相迴路電路於輸出時脈166 MHz時，功率消耗僅有1.45 mW。晶片實作為採用台灣積體電路 (Taiwan Semiconductor Manufacturing Company，TSMC) 0.18 um 1P6M CMOS標準元件庫製程。
本論文的第二個題目介紹植入式生醫系統單晶片之無線負載切換調變電路設計。達成使用無線射頻傳輸介面將晶片內部訊號向外傳輸與晶片外部之控制訊號及功率傳入晶片之目的，增加使用植入式生醫晶片之方便性與安全性。所提出之負載切換調變電路相較於傳統之設計更加省電與節省面積，使植入式生醫晶片之設計功率分配更具彈性。晶片實作為採用TSMC 0.35 um 2P4M CMOS製程。無線傳輸介面採用PCB板與離散元件實作。

The first topic of this thesis is to propose a design of an all-digital low–power PLL (ADPLL). This design is implemented by only using standard cell library. The design cycle is effectively reduced. Furthermore, the portability and reusability of the proposed design is significantly raised. The large power consumption, glitch hazards, and timing violations of prior ADPLL designs are avoided by the proposed control method and modified DCO with multiplexers. The proposed design is implemented by only using the standard cell library of TSMC (Taiwan Semiconductor Manufacturing Company) 0.18 um 1P6M CMOS process. The feature of power saving is verified by measurement, which shows that the power consumption of the proposed ADPLL is merely 1.45 mW at 166 MHz output.
The second topic of this thesis is a load shift keying wireless modulator circuit for implantable biomedical SOC. We successfully realize data and power transmission between outer controller and an implantable chip via wireless RF transmission interface. The convenience and the safety of using the implantable biomedical chip are significantly improved. The proposed on-chip LSK modulator consumes less power and area than those of traditional designs. Hence, the design margin of the implantable biomedical chip will be relaxed. The proposed LSK modulator is implemented with TSMC 0.35um 2P4M mixed-signal process. The proposed wireless RF transmission interface is implemented on PCB with discrete components.

摘要 I
Abstract II
目錄 III
圖目錄 VI
表目錄 IX
第一章 簡介 1
1.1 論文動機 1
1.2 先前文獻探討 3
1.2.1 鎖相迴路 3
1.2.2 負載切換調變電路 4
1.3 論文大綱 4
第二章 全數位元件之低功率鎖相迴路設計 6
2.1 簡介 6
2.2 原理說明 7
2.3 電路架構設計 8
2.3.1 相位頻率偵測器 8
2.3.2 數位控制震盪器 11
2.3.3 降低功率控制電路 14
2.3.4 除頻電路 17
2.3.5 結論 17
2.4 測試考量 18
2.5 模擬結果 19
2.5.1 模擬波形 19
2.5.2 晶片規格 22
2.5.3 規格比較 23
2.6 晶片量測 24
2.6.1 實測結果 24
2.6.2 設計規格與實測結果比較 26
2.6.3 量測後討論 27
2.6.4 改善方法 28
2.6.5 晶片照相圖 29
第三章 植入式系統單晶片之無線負載切換調變電路設計 31
3.1 簡介 31
3.2 原理說明 32
3.3 電路架構設計 33
3.3.1 外部感應電路 34
3.3.2 感應連結方程式 36
3.3.3 內部感應電路 37
3.3.4 負載切換調變電路 38
3.3.5 結論 40
3.4 測試考量 40
3.5 模擬結果 41
3.5.1 模擬波形 41
3.5.2 電路規格 43
3.6 量測結果 44
3.6.1 量測方法 44
3.6.2 設計規格與實測結果 45
3.6.3 量測後討論與改善方法 48
3.6.4 晶片照相圖 49
第四章 結論與相關成果 51
參考文獻 53

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