本論文包含兩個主題，第一個主題是ZigBee 868/915 MHz 頻帶之實體層傳送接收器，第二個主題是數位電視地面廣播解調器之同步設計。
第一個主題包含模擬及硬體設計，此晶片為應用於IEEE Std 802.15.4 無線個人區域網路標準之實體層設計，包含868/915 MHz 頻帶的傳送端與接收端的電路實現，在時脈2.4 MHz 的量測功率最大為144 µW，符合低功率設計的需求。
第二個主題主要包含DVB-T 基頻傳送端的簡介、等效通道模型與接收端解調器之同步設計及模擬。接收端的演算法包括符元時間同步、頻率偏移的估算與補償及散佈性嚮導訊號同步。

This thesis includes two topics. The first topic is a 868/915 MHz band ZigBee physical layer design. The second topic is a synchroniza- -tion design of DVB-T demodulators.
The first topic includes simulations and a hardware design. This chip is a physical layer design for IEEE Std 802.15.4 standard applications, including both a transmitter and a receiver for 868/915 MHz band. The measurement of the maximum power is about 144 µW at 2.4 MHz. This chip is proved to be compliant with a low power consumption requirement.
The second topic mainly includes an introduction of the DVZB-T transmitter, equivalent channel model, a demodulation design of the receiver and simulations. The algorithms of the receiver include symbol timing synchronization, frequency offset estimation and its compensation and scattered pilots synchronization.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章 簡介 1
1.1 前言 1
1.2 研究動機 2
1.3 相關技術及文獻探討 3
1.3.1 ZigBee之相關技術及文獻探討 3
1.3.2 數位電視之相關技術及文獻探討 5
1.4 論文架構 6
第二章 ZigBee 868/915 MHz 頻帶之實體層傳接器 7
2.1 ZigBee簡介 7
2.2 ZigBee 868/915 MHz實體層規格 8
2.3 ZigBee 868/915 MHz傳送端設計 10
2.4 ZigBee 868/915 MHz接收端設計 12
2.4.1 ZigBee 868/915 MHz系統模擬 12
2.4.2 ZigBee 868/915 MHz系統架構 15
2.5 模擬與量測 21
2.5.1 傳送端與接收端模擬結果 21
2.5.2 傳送端與接收端量測結果 24
2.6 晶片佈局 27
2.7 晶片規格與結論 29
第三章 數位電視地面廣播解調器之同步設計 30
3.1 DVB-T傳送端架構 30
3.1.1 Source Coding and Multiplexing 31
3.1.2 通道編碼 (Channel Coding) 31
3.1.3 調變 (Modulation) 39
3.2 通道模型 (Channel Model) 44
3.3 DVB-T接收端解調器同步設計及模擬 51
3.3.1 符元時間同步(Symbol Timing Sync) 52
3.3.2 載波頻率偏移補償(CFO Compensation) 55
3.3.3 散佈性嚮導訊號同步(Scattered Pilots Sync) 57
第四章 結論與展望 59
參考文獻 60

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