本篇論文主要是提出和探討四項新型埋入氧化層結構之多晶矽薄膜電晶體之特性。有鑒於傳統多晶矽薄膜電晶體的缺點，例如漏電流、次臨界擺幅、浮體效應（屈膝效應）、自我加熱效應和短通道效應，我們提出並製作的四種新型埋入氧化層結構之多晶矽薄膜電晶體，經過元件實作及模擬的結果證明可以改善上述之缺點，其結構特徵和電性如下： 1.具多重/雙重基體溝渠(body-trench)特性之元件;此結構改良自傳統多晶矽薄膜電晶體之平坦埋入氧化層結構，可以有效地降低元件off狀態的漏電流高達70%。尤其適用於多晶矽薄膜電晶體，同時亦不會衰減其on狀態的電流。原因在於基體溝渠結構可以改變並延長傳統背向介面(back-interface)漏電流的路徑。此外，我們亦針對此結構做溫度(最高攝氏100度)和應力(最長10000秒)的可靠度實驗。我們發現，雖然其各項電性的衰減幅度比較快，但是仍然優於傳統元件。更重要的是，我們發現此多重/雙重基體溝渠元件具有很大的潛力可以作為單一電晶體之動態隨機存取記憶體(1T-DRAM)。實驗證實，在特定的偏壓條件下(寫入和抹除)，可以造成臨界電壓大幅度的位移，進而得到明顯的規劃視窗（Programming Window）。 2.具基體通道阻絕特性之元件;此結構係利用自我對準技術將阻絕氧化層分別形成於汲極和源極下方。不但可以改善傳統的多晶矽嚴重漏電流問題，同時也預期可以避免因多晶矽通道縮小其膜厚所造成臨界電壓不穩定的問題。 3.具浮體接點(body-tie)特性之元件；此結構提出改良傳統接觸窗光罩圖形的位置，應用於底部閘極多晶矽薄膜電晶體時可以輕易而有效地製作浮體接點，改善傳統電晶體常見的屈膝效應並降低元件off狀態的漏電流。 4.具非連續的埋入氧化層特性之元件；此結構應用了局部場氧化層技術製作出薄膜電晶體之非連續埋入氧化層結構，並將元件製作在局部場氧化層之上，此結構之元件在電性的表現上可以有效地解決傳統元件的屈膝效應和自我加熱效應，且製程簡單而可行，完全匹配傳統CMOS製程。

This thesis is mainly proposed and discussed the characteristics of polycrystalline silicon thin film transistor putting forward and probing into four kinds of novel buried-oxide structures. Because of the shortcoming of the traditional polycrystalline silicon thin film transistor, like leakage current (On/Off state current), subthreshold swing, floating body effect (kink effect), self-heating effect, and short channel effect etc.. Thus, we propose and fabricate four kinds of novel structural polycrystalline silicon thin film transistors that are involved in the following, indicating to improve the critical issues of polycrystalline silicon thin film transistor mentioned above. 1. We propose and fabricate the multiple/dual trenched-body polycrystalline silicon thin film transistor. This proposed structure is demonstrated to obviously suppress the off-state leakage up to 70% reduction, comparing with the conventional device. Also, we survey the reliability of this proposed device included temperature and DC hot-carrier stress effects. We found that the trenched-body TFTs perform more rapid degradation than the conventional TFT does after the temperature and stress durations, but their electrical characteristics are still superior to the conventional counterparts. Importantly, we demonstrate that this proposed device have a dramatic potential to be a novel capacitorless 1T-DRAM, because of its large floating-body-charge storages. As the experiment, the large threshold voltage shift is examined apparently after a certain write and erase operations, leading to a manifest programming window. 2. We propose and fabricate the block-oxide polycrystalline silicon thin film transistor. This proposed structure can not only improve the leakage issue of conventional device seriously, but also avoid fluctuating threshold voltage attributed from the ultra-thin film effect. 3. We propose and fabricate the floating-body contact polycrystalline silicon thin film transistor. This structure is modified by the conventional contact window in order to effectively improve the kink effect, utilizing the bottom gate polycrystalline silicon thin film transistor. 4. Finally, we propose and simulate the non-continuous buried layer polycrystalline silicon thin film transistor. This structure built upon the field oxidation layer can effectively improve the self-heating effect and kink effect. Furthermore, this structure is simple to fabricate, practical, and completely compatible on CMOS technology.

Chapter 1 Introduction ------------------------------------------------------------ 1
1.1 Overview of polycrystalline silicon thin-film transistor-----------------------------1
1.2 Poly-Si thin film technologies-----------------------------------------------------------2
1.3 Typical issues of Poly-Si TFTs ---------------------------------------------------------5
1.4 Poly-Si TFT’s applications------------------------------------------------------------ 10
1.5 Previous studies of novel TFTs/SOIs structures ----------------------------------- 11
1.6 Motivation------------------------------------------------------------------------------- 14
References------------------------------------------------------------------------------- 17
Chapter 2 Electrical Characteristics of Polysilicon Thin-Film Transistor for Simulating Physical Model ------------------------------------ 25
2.1 Introduction ----------------------------------------------------------------------------- 25
2.2 Principle of physical modeling ------------------------------------------------------- 26
References--------------------------------------------------------------------------------34
Chapter 3 Polysilicon Thin-Film Transistor Built on a Multiple / Dual Trench Body -------------------------------------------------------- 35
3.1 Motivation------------------------------------------------------------------------------- 35
3.2 Device fabrication --------------------------------------------------------------------- 36
3.3 Lateral / vertical electric field analysis-----------------------------------------------38
3.4 Experimental result and discussion---------------------------------------------------39
3.5 Summary -------------------------------------------------------------------------------- 44
References------------------------------------------------------------------------------- 45
Chapter 4 Reliability of Polysilicon Thin-Film Transistor with Trench Body under Temperature and Stressing ----------------------- 55
4.1 Motivation ------------------------------------------------------------------------------ 55
4.2 Device fabrication --------------------------------------------------------------------- 56
4.3 Reliability measurement and analysis----------------------------------------------- 56
4.4 Summary -------------------------------------------------------------------------------- 65
References ------------------------------------------------------------------------------ 67
Chapter 5 The Back-Gate Effect and 1T-DRAM performance of Polysilicon Thin-Film Transistor with Trench Body -------- 76
5.1 Motivation ------------------------------------------------------------------------------ 76
5.2 Device fabrication --------------------------------------------------------------------- 78
5.3 Result and discussions: a novel 1T-DRAM cell with back-gate bias ----------- 78
5.4 Summary -------------------------------------------------------------------------------- 83
References ------------------------------------------------------------------------------ 84
Chapter 6 Polysilicon Thin-Film Transistor Built on Self-aligned Block Oxide ------------------------------------------------------------------- 93
6.1 Motivation ------------------------------------------------------------------------------ 93
6.2 Device fabrication --------------------------------------------------------------------- 95
6.3 Experimental result and discussion --------------------------------------------------96
6.4 Summary -------------------------------------------------------------------------------101
References ----------------------------------------------------------------------------- 103
Chapter 7 Smart Body Tie on the Bottom Gate polysilicon Thin Film Transistor
7.1 Motivation ----------------------------------------------------------------------------- 113
7.2 Device fabrication -------------------------------------------------------------------- 115
7.3 Simulation result and characterization --------------------------------------------- 116
7.4 Experimental result and discussion ------------------------------------------------ 120
7.5 Summary ------------------------------------------------------------------------------- 123
References ----------------------------------------------------------------------------- 124
Chapter 8 Polysilicon Thin-Film Transistor Built on Non-continuous Buried Insulator ---------------------------------------------------- 134
8.1 Motivation ----------------------------------------------------------------------------- 134
8.2 Process simulation -------------------------------------------------------------------- 135
8.3 Simulation result ---------------------------------------------------------------------- 136
8.4 Summary ------------------------------------------------------------------------------- 139
References ----------------------------------------------------------------------------- 140
Chapter 9 Analysis of Polysilicon Thin Film Transistor with NH3 Diffusing Treatment --------------------------------------------- 146
9.1 Motivation ----------------------------------------------------------------------------- 146
9.2 Poly-silicon thin film preparation -------------------------------------------------- 147
9.3 Experimental result and discussion of device ------------------------------------ 149
9.4 Summary ------------------------------------------------------------------------------- 151
References ----------------------------------------------------------------------------- 153
Chapter 10 Conclusion --------------------------------------------------------- 163
Chapter 11 Future work -------------------------------------------------------- 168

Chapter 1
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Chapter 2
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Chapter 3
1. A. G. Lewis, D. D. Lee and R. H. Bruce, “Poly silicon TFT circuit design and performance,” IEEE Journal Solid State Circuits, vol. 27, pp. 1833-1842, 1992.
2. R. E. Proand, R. S. Misage and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 36, pp. 1915-1922, 1989.
3. J. G. Fossum, A. Ortiz-Conde, H. Shichijo and S. K. “Banerjee, Anomalous leakage current in LPCVD polysilicon MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-32, pp. 1878-1884, 1985.
4. K. R. Olasupo and M. K. Hatalis, “Leakage current mechanism in sub-micron polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 43, pp. 1218-1223, 1996.
5. S. D. Brotherton, J. R. Ayres and M. J. Trainor, “Control and analysis of leakage currents in poly-Si thin-film transistors,” J. Appl. Phys., vol. 79(2), pp. 895-904, 1996.
6. B. H. Min, C. M. Park and M. K. Han, “A novel offset gated polysilicon thin film transistor without an additional offset mask,” IEEE Electron Device Letters, vol. 16, pp. 161-163, 1995.
7. J. h. Park and O. Kim, “A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process,” IEEE Electron Device Letters, vol. 26, pp. 249-251, 2005.
8. M. Hatano, H. Akimoto and T. Sakai, “A Novel Self-aligned Gate-overlapped LDD Poly-Si TFT with High Reliability and Performance,” IEDM Tech. Dig., pp. 523-526, 1997.
9. K. R. Olasupo, W. Yarbrough and M. K. Hatalis, “The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 43, pp. 1306-1308, 1996.
10. K. Tanaka, K. Nakazawa, S. Suyama, and K. Kato, “Characteristics of field-induced-drain (FID) poly-si TFT’s with high ON/OFF current ratio,” IEEE Trans. Electron Devices, vol. 39, pp. 916-919, 1992.
11. S. Yamada, S. Yokoyama, and M. Koyanagi, “Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT,” IEDM Tech. Dig., pp. 859-862, 1990.
12. C. A. Dimitriadis and D. H. Tassis, “On the threshold voltage and channel conductance of polycrystalline silicon thin-film transistors,” J. Appl. Phys., vol. 79, no. 8, pp. 4431-4437, 1996.
13. M. Hack, I-W. Wu, T. J. King and A. G. Lewis, “Analysis of leakage currents in poly-silicon thin film transistors,” IEDM Tech. Dig., pp. 385-388, 1993.
14. H. K. Lim and J. G. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s”, IEEE Trans. Electron Devices, vol. ED-30, pp. 1244-1251, 1983.
15. N. Shigyo, S. Fukuda, T. Wada, K. Hieda, T. Hamamoto, H. Watanabe, K. Sunouchi and H. Tango, “Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1-4-μm-width MOSFETs,” IEEE Trans. Electron Devices, vol. 35, pp. 945-951, 1988.
Chapter 4
1. W. Benzarti, F. Plais, A. D. Luca and D. Pribat, “Compact analytical physical-based model of LTPS TFT for active matrix displays addressing circuits simulation and design,” IEEE Trans. Electron Devices, vol. 51, no. 3, pp.345-350, 2004.
2. G. Lewis, D. D. Lee and R. H. Bruce, “Polysilicon TFT circuit design and performance,” IEEE J. Solid State Circuits, vol. 27, p1833–1842, 1992.
3. Ling Wang, Tor A. Fjeldly, Benjamin Iniguez, Holly C. Slade and Michael Shur, “Self-heating and kink effects in a-Si :H thin film transistors”, IEEE Trans. Electron Devices, vol. 47, pp. 387-397, 2000.
4. G. Fortunato, A. Pecora, I. Policicchio, F. Plais and D. Pribat, “Kinetics of interface state generation induced by hot carriers in n-channel polycrystalline silicon thin-film transistors”, Jpn. J. Appl. Phys., vol. 35, pp. 1544-1547, 1996.
5. L. Mariucci, G. Fortunato, R. Carluccio, A. Pecora, S. Giovannini, and F. Massussi, L. Colalongo and M. Valdinoci, “Determination of hot-carrier induced interface state density in polycrystalline silicon thin-film transistors”, J. Appl. Phys., vol. 84, pp. 2341-2348, 1998.
6. Huang-Chung Cheng, Fang-Shing Wang and Chun-Yao Huang, “Effects of NH3 plasma passivation on n-channel polycrystalline silicon thin-film transistors”, IEEE Trans. Electron Devices, vol. 44, pp. 64-68, 1997.
7. S. K. Lai, “Interface trap generation in silicon dioxide when electrons are captured by trapped holes”, J. Appl. Phys., vol. 54, pp. 2540-2546, 1983.
8. D. J. DiMaria, D. A. Buchanan, J. H. Stathis and R. E. Stahlbush, “Interface states induced by the presence of trapped holes near the silicon–silicon-dioxide interface”, J. Appl. Phys., vol. 77, pp. 2032, 1995.
9. D. A. Buchanan and D. J. DiMaria, “Interface and bulk trap generation in metal-oxide-semiconductor capacitors”, J. Appl. Phys., vol. 67, pp. 7439-7452, 1990.
10. Michael L. Chabinyc, Jeng-Ping Lu, Robert A. Street, Yiliang Wu, Ping Liu and Beng S. Ong, “Short channel effects in regioregular poly(thiophene) thin film transistors”, J. Appl. Phys., vol. 96, pp. 2063-2070, 2004.
11. C. A. Dimitriadis and P. A. Coxon, “Effects of temperature and electrical stress on the performance of thin-film transistors fabricated from undoped low-pressure chemical vapor deposited polycrystalline silicon”, Appl. Phys. let., vol. 54, pp. 620-622, 1989.
12. B. Iniguez, L. Wang, T. A. Fjeldly, Y. S. Shur and H. Slade, “Thermal, Self-heating and Kink Effects in a-Si:H Thin Film Transistors”, IEDM Tech. Dig.,, pp. 879-882, 1998.
13. F. Lemmi and Robert A. Street, “The leakage currents of amorphous silicon thin-film transistors: injection currents, back channel currents and stress effects”, IEEE Trans. Electron Devices, vol. 47, pp. 2404-2409, 2000.
14. H. C. Slade and M. S. Shur, “Analysis of bias stress on unpassivated hydrogenated amorphous silicon thin-film transistors”, IEEE Trans. Electron Devices, vol. 45, pp. 1548-1533, 1998.
15. F. V. Farmakis, C.A. Dimitriadis, J. Brini, G. Kamarinos, V.K. Gueorguiev and Tz. E. Ivanov, “Hot-carrier phenomena in high temperature processed undoped-hydrogenated n-channel polysilicon thin film transistors (TFT’s),” Solid-State Electron., vol. 43, pp. 1259, 1999.
16. G. Fortunato, A. Pecora, G. Tallarida, L. Mariucci, C. Reita and P. Migliorato, “Hot carrier effects in n-channel poly crystalline silicon thin-film transistors : a correlation between off-current and transconductance variations”, IEEE Trans. Electron Devices, vol. 41, pp. 340-346, 1994.
17. F. V. Farmakis, J. Brini, G. Kamarinos and C. A. Dimitriadis, “Anomalous turn-on Voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors”, IEEE Electron Device Letters, vol. 22, pp. 74-76, 2001.
18. F. V. Farmakis, C. A. Dimitriadis, J. Brini, G. Kamarinos, V. K. Gueorguiev and Tz. E. Ivanov, “Interface state generation during electrical stress in n-channel undoped hydrogenated polysilicon thin-film transistors”, Electron letters, vol. 34, 1998.
19. I. W.Wu, W. B.Jackson, T. Y. Huang, A. G. Lewis and A. Chiang, “Mechanism of device degradation in n- and p-channel polysilicon TFTs by electrical stressing”, IEEE Electron Device Letters, vol. 11, pp. 167-170, 1990.
Chapter 5
1. H. Oh , H. Choi., T. Sskaguchi, and J. C. Shim, “Novel silicon on insulator metal oxide semiconductor field effect transistors with buried back gate”, Jpn. J. Appl. Phys., vol. 43, pp. 2140-2144, 2006.
2. K. Hayamaa K. Takakura, S. Okada, T. Kudou, H. Ohyama, J.M. Rafı, J.A. Martino, A. Mercha, E. Simoen and C. Claeys, “Investigation of back gate interface states by drain current hysteresis in PD-SOI n-MOSFETs”, Physica B: Condensed Matter, vol. 376-377, pp. 416-419, 2006.
3. Y. Yamada, H. Oh, T. Sskaguchi, T. Fukushima and M. Koyanagi, “Characteristics of silicon-on-low k insulator metal oxide semiconductor field Effect transistor with metal back gate”, Jpn. J. Appl. Phys., vol. 45, pp. 3040-3044, 2006.
4. H. S. Jeong W.S. Yang, Y.S. Hwang, C.H. Cho, S. Park, S.J. Ahn, Y.S. Chun, S.H. Shin, S.H. Song, J.Y. Lee, S.M.J ang, C.H. Lee, J.H. Jeong, M.H. Cho, J.K. Lee and K. Kim, “Highly manufacturable 4Gb DRAM using 0.11 um DRAM technology,” IEDM Tech. Dig., pp. 353-356, 2000.
5. A. Nitayama, Y. Kohyama and K. Hieda, “Future directions for DRAM memory cell technology”, IEDM Tech. Dig., pp. 355-358, 1998.
6. S. Okhonin, M. Nagoga, J. M. Sallese and P. Fazan, “A SOI Capacitor-less 1T-DRAM Concept”, IEEE international SO1 Conference, pp. 153-154, 2001.
7. P. C. Fazan, S. Okhonin, M. Nagoga and J.-M. Sallese, “A Simple 1-Transistor Capacitor-Less memory cell for high performance embedded DRAMs”, IEEE custom integrated circuits conference, pp. 99-102, 2002.
8. A. Nitayama, T. Ohsawa and T. Hamamoto, “Overview and future challenge of floating body cell (FBC) technology for embedded applications”, IEDM Tech. Dig., pp. 1-3, 2006.
9. K. Inoh, K. Inoh, T. Shino, H. Yamada, H. Nakajima, Y. Minami, T. Yamada, T. Ohsawa, T. Higashit, K. Fujila, T. Ikehashi, T. Kajiyama, Y. Fukuzumi, T. Hamamoto and H. Ishiuchi, “FBC (Floating Body Cell) for embedded DRAM on SOI”, Symposium on VLSI Tech. Dig., pp. 63-64, 2003.
10. T. Tanaka, E. Yoshida and T. Miyashita, “Scalability study on a Capacitorless 1T-DRAM: from single-gate PD-SO1 to double-gate FinDRAM”, IEDM Tech. Dig., pp. 919-922, 2004.
11. T. Shino, T. Ohsawa, T. Higashi, K. Fujita, N. Kusunoki, Y. Minami, M. Morikado, H. Nakajima, K. Inoh, T. Hamamoto and A. Nitayama, “Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell”, IEEE Trans. Electron Devices, vol. 52, pp. 2220-2226, 2005.
12. J.-T. Lin and K.-D. Huang, “Non-classical polysilicon thin-film transistor with symmetric trenched body”, Electronics Letters, vol. 43, 2007, pp. 1390-1392, 2007.
13. J.-T. Lin and K.-D. Huang, “A novel polysilicon thin-film transistor with multi-trenched body for suppressing off-State leakage”, IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Tainan, Taiwan, Dec. 20-22, 2007.
14. Y. Kaneko, K. Tsutsui and T. Tsukada, “Back-bias effect on the current-voltage characteristics of amorphous silicon thin-film transistors”, Journal of Non-Crystalline Solids, vol. 149, pp. 264-268, 1992.
15. Y. Nakajima, H. Tomita, K. Aoto, N. Ito, T. Hanajiri, T. Toyabe, T. Morikawa and T. Sugano, “Characterization of trap states at silicon-on-insulator (SOI)/buried oxide (BOX) interface by back gate transconductance characteristics in SOI MOSFETs”, Jpn. J. Appl. Phys., vol. 42, pp. 2004-2008, 2003.
16. S. Schwantes, T. Florian, M. Graf, F. Dietz and V. Dudek, “Analysis of the back gate effect on the breakdown behaviour of SOI LDMOS transistors”, IEEE 34th European Solid-State Device Research conference (ESSDERC), pp. 253-256, 2004.
Chapter 6
1. H. Wang, M. Chan, S. Jagar, V. M. C. Poon and M. Qin, “Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method,” IEEE Trans. Electron Devices, vol. 47, pp. 1580-1586, 2000.
2. Z. Xiong, H. Liu, C. Zhu and J. K. O. Sin, “A new polysilicon CMOS self-aligned double-gate TFT technology,” IEEE Trans. Electron Devices, vol. 52, pp. 2629-2633, 2005.
3. Y. C. Wu, C. Y. Chang, T.C. Chang, P. T. Liu, C.S. Chen and C.H. Tu, “High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels,” IEDM Tech. Dig.,, pp. 777-779, 2004.
4. J. R. Ayres, S. D. Brotherton, D. J. McCulloch and M. J. Trainor, “Analysis of drain field and hot carrier stability of poly-si thin film transistors,” Jpn. J. Appl. Phys., vol. 37, pp. 1801-1808, 1998.
5. S. Yamada, S. Yokoyama and M. Koyanagi, “Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT,” IEDM Tech. Dig., pp. 859-862, 1990.
6. M. Miyasaka, T. Komatus, W. Itoh, A. Yamaguchi and H. Ohshima, “Effects of semiconductor thickness on poly-crystalline silicon thin film transistors,” Jan. J. Appl. Phys., vol. 35, pp. 923-929, 1996.
7. S. Sleva and Y. Taur, “The influence of source and drain junction depth on the short-channel effect in MOSFETs,” IEEE Trans. Electron Devices,” vol. 52, pp. 2814-2816., 2005
8. S. Z. Luan, H. X. Liu and Y. Hao, “The influence of source and drain junction depth on the sub-50nm MOSFET devices,” 8th Int. Conference on Solid-State and Integrated-Circuit Technology, pp. 263-265, 2006.
9. A. G. Lewis, I. W. Wu, T. Y. Huang, M. Koyanagi, A. Chiang and R. H. Bruce, “Small geometry effects in n- and p-channel polysilicon thin film transistors,” IEDM Tech. Dig., pp. 260-263, 1998.
10. A. G. Lewis, T. Y. Huang, I. W. Wu, R. H. Bruce and A. Chiang, “Physical mechanisms for short channel effects in polysilicon thin films transistors,” IEDM Tech. Dig., pp. 349-352, 1989.
11. R. K. Watts and J. T. C. Lee, “Tenth-micron polysilicon thin-film transistors,” IEEE Electron Device Letters, vol. 14, pp. 515-517, 1993.
12. J. Lee, K. Kim, J. H. Kim and S. Im, “Optimum channel thickness in pentacene-based thin-film transistors,” Appl. Phys. Lett., vol. 82, pp. 4169-4171, 2003.
13. M. Miyasaka, T. Komatus, W. Itoh, A. Yamaguchi and H. Ohshima, “Effects of semiconductor thickness on poly-crystalline silicon thin film transistors,” Jan. J. Appl. Phys. vol. 35, pp. 923-929, 1996.
14. Y. K. Choi, D. Ha, T. J. King and C. Hu, “Threshold voltage shift by quantum confinement in ultra-thin body device”, IEEE 58th Device Research Conference, pp. 85-86, 2001.
15. N. Shigyo, S. Fukuda, T. Wada, K. Hieda, T. Hamamoto, H. Watanabe, K. Sunouchi and H. Tango, “Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1-4-μm-width MOSFETs,” IEEE Trans. Electron Devices, vol. 35, pp. 945-951, 1988.
16. S. D. Brotherton, J. R. Ayres and M. J. Trainor, “Control and analysis of leakage currents in poly-Si thin-film transistors J. Appl. Phys., vol. 79(2), pp. 895-904, 1996.
Chapter 7
1. M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora and I. Policicchio, “Floating body effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 44, no. 12, pp. 2234-2241, 1997.
2. J. R. Ayres, S. D. Brotherton, D. J. McCulloch and M. J. Trainor, “Analysis of drain field and hot carrier stability of poly-Si thin film transistors”, Jpn. J. Appl. Phys., vol. 37, pp. 1801-1808, 1998.
3. S. D. Brotherton, J. R. Ayres and M. J. Trainor, “Control and analysis of leakage currents in poly-Si thin-film transistors,” J. Appl. Phys., vol. 79, pp. 895, 1996.
4. M. Miyasaka, T. Komatsu, W. Itoh, A. Yamaguchi and H. Ohshima, “Effects of semiconductor thickness on poly-crystalline silicon thin film transistors,” Jpn. J. Appl. Phys, vol.35, pp. 923-929, 1996.
5. Y. H. Koh, J. H. Choi, M. H. Nam and J. W. Yang, “Body-contacted SOI MOSFET structure with fully bulk CMOS compatible layout and process,” IEEE Electron Device Lett., vol. 18, pp. 102-104, 1997.
6. M. Yoshimi, M. Terauchi, A. Nishiyama, O. Arisumi, A. Murakoshi, K. Matsuzawa, N. Shigyo, S. Takeno, M. Tomita, K. Suzuki, Y. Ushiku and H. Tango, “Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si1-xGex source structure,” IEEE Trans. Electron Devices, vol. 44, pp. 423, 1997.
7. V. M. C. Chen and J. C. S. Woo, “Tunneling source-body contact for partially-depleted SOI MOSFET,” IEEE Trans. Electron Devices, vol. 44, pp. 1143, 1997.
8. B. W. Min and M. Mendicino, “Effective body contact in SOI devices by partial trench isolated body-tied (PTIBT) structure,” IEEE Semiconductor Device Research Symposium, pp. 469-472, 2001.
9. P. Y. Kuo, T. S. Chao and T.F. Lei, “Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure,” IEEE Electron Devices Letters, vol. 25, pp. 634, 2004.
10. M. Matloubian, “Smart body contact for SOI MOSFETs,” Proceedings of IEEE SOI Conference, pp.128-129, 1989.
11. P. Y. Kuo, T. S. Chao and T. F. Lei, “Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure,” IEEE Electron Devices Letters, vol. 25, pp. 634-636, 2004.
12. J. T. Lin and S. T. Lin, “Fabrication and simulation of the SOI MOSFET with smart body tie”, NSYSUEE, Kaohsiung, Taiwan, July 2006.
13. L. Chang, S. Tang, T. J. King, J. Bokor and C. Hu, “Gate length scaling and threshold voltage control of double-gate MOSFETs,” IEDM Tech. Dig., pp. 719-722, 2000.
14. J. T. Lin, K. D. Huang and S. F. Hu, “A novel bottom gate polysilicon thin-film transistor with smart body tie,” 25th international conference on microelectronics, pp. 346-349, 2006.
Chapter 8
1. S. Jagar, M. Chan, M.C. Poon, H. Wang, M. Qin, P. K. KO and Y. Wang, “Single grain thin-film-transistor (TFT) with SO1 CMOS performance formed by Metal-Induced-Lateral-Crystallization,” IEDM Tech. Dig., pp. 293-296, 1999.
2. P. Su, K. Goto, T. Sugii and C. Hu, “Self-heating enhanced impact ionization in SOI MOSFETs”, IEEE International SO1 Conference, pp. 31-32, 2001.
3. M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora and I. Policicchio, “Floating body effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 44, pp. 2234-2241, 1997.
4. J. R. Ayres, S. D. Brotherton, D. J. McCulloch and M. J. Trainor, “Analysis of drain field and hot carrier stability of poly-Si thin film transistors”, Jpn. J. Appl. Phys., vol. 37, pp. 1801-1808, 1998.
5. S. Yamada, S. Yokoyama, and M. Koyanagi, “Two-dimensional device simulation for avalanche induced short channel effect in poly-Si TFT”, IEDM Tech. Dig., pp. 859-862, 1990.
6. T. D. Her, P. S. Liu, D. S. Quon, G. P. Li, R. Kjar and J. White, “Parasitic bipolar transistor induced latch and degradation in SOI MOSFET's”, IEEE SOI Conference, pp. 124-125, 1991.
7. J. T. Lin and C. L. Wu, “Fabrication and simulation of the SOI MOSFET with smart body tie”, NSYSUEE, Kaohsiung, Taiwan, July 2006.
8. J. T. Lin, K. D. Huang and C. L. Wu, “An alleviated self-heating poly-Si thin-film transistor built on non-continuing buried insulator,” Electrochemical and Solid-State Letters, 10(3), pp. 107-110, 2006.
9. J. Hui, T. Y. Chiu, S. Wong and W. G. Oldham, “Electrical properties of MOS devices made with SILO technology,” IEDM Tech. Dig., pp. 220-223, 1982.
10. C. J. Glassbrenner and G. A. Slack, “Thermal conductivity of silicon and germaniμm from 3 K to the melting point,” Physical Review, vol. 134, pp. A1058-A1069, 1964.
Chapter 9
1. M. K. Hatalis and D. W. Greve, “Large grain polycrystalline silicon by low-temperature annealing of low-pressure chemical vapor deposited amorphous silicon films,” J. Appl.Phys. , 63(7), p2260-2266, 1988.
2. H. Ikeda, “Surface potential based poly-Si thin-film transistor model for SPICE,” IEDM Tech. Dig., pp. 1-4, 2006.
3. V.W.C. Chan, P.C.H. Chan and C. S. Yin, “The effects of grain boundaries in the electrical characteristics of large grain polycrystalline thin-film transistors,” IEEE Trans. Electron Devices, vol. 49, pp. 1384-1391, 2002.
4. N. T. Golo, F. G. Kuper and T. J. Mouthaan, “Analysis of the Electrical Breakdown in Hydrogenated Amorphous Silicon Thin-Film Transistors,” IEEE Trans. Electron Devices, vol. 49, pp. 1012-1018, 2002.
5. C. K. Yang, T. F. Lei and C. L. Lee, “The combined effects of low pressure NH3-annealing and H2 plasma hydrogenation on polysilicon thin-film transistors,” IEEE Electron Device Lett., vol. 15, pp. 389-390, 1994.
6. H. C. Cheng, F. S. Wang and C. Y. Huang, “Effects of NH3 plasma passivation on n-channel polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 44, pp. 64-68, 1997.