在本論文中，我們主要目的在建立與設計一個像PMOS的NMOS，它雖然是一個NMOS但擁有類似PMOS的特性曲線。它可被應用在低功率高速度，完全只有NMOS構成的單載子互補金氧半(Unipolar CMOS)電路和系統。同時，我們也設計和製作此類的電路和系統。
互補式金氧半(Complementary Metal-oxide semiconductor, CMOS)現今已成為積體電路中最重要的邏輯電路元件，在元件持續微縮的趨勢下，傳統互補式金氧半面臨嚴重短通道效應、正型金氧半(PMOS)需較大面積、和載子移動率不匹配等缺點。在本論文中為了克服這些問題，我們新提出了一個具有抬高本體搭配側壁與嵌入式氧化物之非傳統互補式金氧半，其操作物理機制為貫穿效應，以貫穿電流為主要操作電流，架構為利用負型金氧半(NMOS)去取代傳統互補式金氧半中的正型金氧半(PMOS)，此時傳輸載子皆為電子，成功解決載子移動率不匹配的問題。我們不但可改善傳遞延遲時間，也可使整體操作速度提升，尤其是小至0.5 V之低電源電壓電路與系統。
根據模擬的結果，我們所新設計出的NMOS負載端成功的達到類似正型金氧半的特性。在邏輯閘電路上，利用本論文提出之單載子互補式金氧半所組成之邏輯電路在VDD = 0.5 V時均能夠顯示出正確的邏輯特性，同時我們也驗證本論文之架構可以成功操作在0.3 V 下之靜態隨機存取記憶體。在傳遞延遲時間方面，比起傳統互補式金氧半下降了46 %，整體的評量指標表現則改善了57 %，而環形震盪器的操作頻率相較於傳統更增加了55 %。另外，在製程規劃佈局時，因為驅動端與負載端皆由NMOS所組成，不需要N型井之製程步驟，負載端也不須因載子移動率不同而做寬度的補償，又可以共享輸出電極，將大幅的縮小面積達到23 %。

The aim of this thesis is to develop a PMOS-like NMOS for use in an ultra-low power high speed all-NMOS unipolar CMOS circuits and systems and produce them.
Recently CMOS is the mainstream in integrated circuit and IC industry. In the trend of continuing scale-down of devices, conventional CMOS suffers from serious short channel effect and its PMOS needs width compensation because the mobility of hole and electron is not a good match. In order to solve these issues, we propose a non-classical CMOS with elevated body, spacer and embedded oxide in the thesis. The operation mechanism exploits punch through effect and we use the punch through current as the major current component. The proposed CMOS is composed of two NMOSs. Because of this, the channel carriers are electrons only. After successfully resolving the problem of the carrier mobility mismatch, we not only improve the propagation delay time in CMOS but also the overall operating speed. The improvement will be particularly obvious when the VDD is equal 0.5 V being applied in the circuits and systems.
According to the simulation results, our designed NMOS load can act like a PMOS. The non-classical CMOS achieves completely correct logic characteristic for any logic gates when the VDD is equal 0.5 V. We also verify that our structure can successfully operate static random access memory at 0.3 V. The delay time and the figure of merit of our proposed unipolar CMOS can be reduced 46 % and improved 57 % when compare with the conventional CMOS. Besides, the frequency of ring oscillator can be improved 55 %. In addition, duo to the load and drive transistor are all NMOS, the N-well process is not necessary. The load does not need width compensation because of the mobility problem. In particular, our structure can share the output contact, the fabrication areas can thus be reduced more than 23 %.

論文審定書 i
英文論文審定書 ii
致　謝 iii
摘　要 iv
Abstract v
目 錄 vi
圖目錄 ix
表格目錄 xiv
第一章 導論 1
1.1 研究背景 1
1.2 相關研究論文回顧 3
1.3 動機 8
第二章 傳統互補式金氧半與貫穿效應之操作原理 9
2.1 傳統互補式金氧半反相器 9
2.2 負載線 11
2.3 電壓與電離轉移特性曲線 12
2.4 貫穿效應 14
2.5 利用貫穿效應之互補式金氧半操作原理 16
2.6 單載子傳輸負載線 20
2.7 單載子互補式金氧半電壓與電流轉移特性曲線 23
第三章 元件架構設計與製程步驟 24
第四章 電性討論與結果 26
4.1 物理模型與說明 26
4.2 元件模擬結果 27
4.2.1 抬高本體搭配側壁與雙嵌入氧化物之負型金氧半 27
4.3 數位邏輯電路模擬與應用 50
4.3.1 反或閘(NOR Gate) 50
4.3.2 反及閘(NAND Gate) 54
4.3.3 Pseudo-NMOS之反或閘(Preudo-NMOS-NOR Gate) 57
4.3.4 Pseudo-NMOS之反及閘(Preudo-NMOS-NAND Gate) 60
4.3.5 環形振盪器(Ring Oscillator) 64
4.3.6 互斥或閘(XOR Gate) 65
4.3.7 全加器(Full adder) 68
4.3.8 解碼器(Decoder) 71
4.3.9 乘法器(Multiplier) 74
4.3.10 減法器(Subtractor) 78
4.3.11 多工器(Multiplexers) 81
4.3.12 骨牌CMOS邏輯(Domino CMOS logic) 84
4.3.13 RS正反器(RS Flip flop) 87
4.3.14 D型正反器(D Flip flop) 90
4.3.15 JK正反器(JK Flip flop) 93
4.3.16 數位比較器(Digital Comparator) 96
4.3.17 靜態隨機存取記憶體(Static Random Access Memory, SRAM) 99
4.3.18 靜態隨機存取記憶體之操作模式 102
4.3.19 探討SRAM操作電壓微縮之極限 107
4.3.20 單載子邏輯電路寬度補償原則 110
4.4 環形震盪器操作頻率比較 111
4.5 傳遞延遲時間(Propagation delay time)與評量指標(FOM)比較 114
4.6 抬高本體搭配側壁與雙嵌入氧化物互補式金氧半與傳統互補式金氧半之佈局面積比較 118
4.7 調變閘極功函數對單載子互補式金氧半反相器之影響 119
4.8 單載子互補式金氧半反相器之操作電壓變化 124
4.9 反相器之高位雜訊邊限與低位雜訊邊限探討 125
4.10 側壁厚度造成串聯電阻之討論 128
4.11 元件實作結果與量測 132
第五章 結論與未來展望 135
5.1 結論 135
5.2 未來展望 136
參考文獻 137
附錄 143
A.空乏區寬度計算公式 143
B.閘極控制之空乏區寬度 144
C.平帶電壓 145
個人得獎 146

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