近年來感測元件的功耗在逐漸降低，因此自我供電系統的概念被提出；其中，可利用晶圓廠製程製作的積體化光伏元件是一項研究重點。本論文嘗試利用不同標準晶圓廠CMOS製程節點製作積體化背面照光光伏元件，並藉由元件特性量測與分析找出製作光伏元件的最佳晶圓廠製程。透過不同製程多組元件的量測分析，我們發現光伏元件的轉換效率主要取決短路電流的多寡，所有的製程皆在矽基板厚度150 μm、入射光強度10 mW時展現最大短路電流及最佳光電轉換效率。0.18 μm製程的最佳光電轉換效率為9.67%，0.25 μm製程較前者多出0.11%為9.78%，為三種製程中光電轉換效率最高的製程；而0.35 μm製程的最佳光電轉換效率僅有8.17%，但該製程的光電轉換效率在矽基板的厚度上有高誤差容忍度，從矽基板厚度70 μm到250 μm都還有最高光電轉換效率的八成，以製程良率為考量有極大的優勢。而除了製程、基板厚度及入射光源強度外，短路電流還與兩種參數有關，反射鏡效率以及底P-N接面面積的比例。目前的多晶矽光柵反射鏡設計增加9.9%的短路電流以及10.6%的光電轉換效率；而將底P-N接面面積的比例由85%提高至93%，短路電流會提升9.7%。製程解析度越高，製造價格也越高；因此成本及良率考量優先者，0.35 μm製程是三種製程中的最佳選擇；若對元件效率要求較高則可以考慮0.18 μm製程。由於0.25 μm製程尚無法在單一晶片上進行元件高壓串接且製程昂貴，故暫不建議使用。

Continued developments in reducing the size and power consumption of deeply-scaled CMOS devices have opened the door to self-powered remote systems. The implementation of integrated photovoltaic devices (PVs) using CMOS compatible process has attracted much attentions. This thesis aims to realize and optimize backside-illuminated CMOS photovoltaic devices by using standard foundry bulk CMOS processes in different technology nodes (0.35-, 0.25-, and 0.18-μm). All CMOS PV chips received from the foundries undergo post substrate thinning process to thin the PVs to 150 μm in thickness in order to achieve the highest photocurrent collection efficiency under 10-mW illumination. The PV layout designs for respective technology nodes are optimized based on the limitation and regulation of each process. As-realized CMOS PVs by 0.35-, 0.25-, and 0.18-μm bulk CMOS processes achieve an ultimate efficiency of 8.17%, 9.78%, and 9.67%, respectively. Nevertheless, the CMOS PVs made by 0.35-μm bulk CMOS have higher tolerance on substrate thickness variation with a drop on efficiency of only 20% for a substrate thickness of 70 and 250 μm. In addition, the realization of backside polysilicon grating reflectors in CMOS PVs will boost the ultimate efficiency by 10.6% due to the light trapping effect. Overall, the CMOS PVs realized in 0.18-μm and 0.25-μm bulk CMOS provide the comparable conversion efficiency and is better than the devices made in 0.35-μm bulk CMOS. But if you take the cost into consideration, the CMOS PVs realized in 0.35-μm is a good choice in terms of dollar per watt.

中文審定書 i
英文審定書 ii
致謝 iii
摘要 iv
Abstract v
內容目錄 vi
圖目錄 viii
表目錄 xi
發表列表 xii
第一章 序論 1
1.1 前言 1
1.2 研究動機: 2
1.3 文獻回顧 7
1.4 論文架構 10
第二章 光伏元件特性簡介 11
2.1 光伏元件工作原理 11
2.2 光伏元件參數簡介 13
2.2.1 開路電壓 14
2.2.2 短路電流 15
2.2.3 填充因子 15
2.2.4 轉換效率 15
2.3 影響元件特性之因素 16
2.3.1 受光面的反射損失(Reflection loss): 16
2.3.2 載子複合損失(Recombination loss): 16
2.3.3 電阻效應(Resistive effect): 16
2.3.4 元件之環境溫度 19
第三章 製程節點及量測儀器介紹 21
3.1 在CMOS 製程架構下之背面照光光伏元件架構 21
3.2 不同製程節點的特性差異 24
3.3 元件基板研磨製程 26
3.4 量測系統架構 28
3.4.1 光源強度控制子系統 29
3.4.2光伏元件參數量測及計算程式 32
第四章 不同製程節點之晶片設計與量測結果 34
4.1 標準0.35 μm CMOS製程不同元件設計之比較 34
4.2 標準0.18 μm CMOS製程不同元件設計之比較 41
4.3 標準0.25 μm CMOS製程元件設計 51
4.4 製作積體化光伏元件的最佳製程 54
第五章 結論與未來方向 56
5.1 結論 56
5.2 未來研究方向 57
參考文獻 58
附錄 61

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